Abstract
This paper determines correctness and timing properties for structured parallel programs on x86-64 multicores. Multicore architectures are increasingly common, but real architectures have unpredictable timing properties, and commonly used relaxed-memory concurrency models mean that even functional correctness is not obvious. This paper takes a rigorous approach to correctness and timing properties, examining common locking protocols from first principles, and extending this through queues to structured parallel constructs. We prove functional correctness and derive simple timing models, extending these for the first time from low-level machine operations to high-level parallel patterns. Our derived high-level timing models for structured parallel programs allow us to accurately predict upper bounds on program execution times on x86-64 multicores.
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Notes
- 1.
We will ignore shared cache here, since it does not have a significant impact on the proofs.
- 2.
In the sense that locks are not visible to the programmer, rather than they are not used by the hardware.
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Acknowledgements
This work has been partially supported by the EU Horizon 2020 grant “RePhrase: Refactoring Parallel Heterogeneous Resource-Aware Applications – a Software Engineering Approach” (ICT-644235), by COST Action IC1202 (TACLe), supported by COST (European Cooperation in Science and Technology), and by EPSRC grant EP/M027317/1 “C\({}^3\): Scalable & Verified Shared Memory via Consistency-directed Cache Coherence”.
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Hammond, K., Brown, C., Sarkar, S. (2016). Timing Properties and Correctness for Structured Parallel Programs on x86-64 Multicores. In: van Eekelen, M., Dal Lago, U. (eds) Foundational and Practical Aspects of Resource Analysis. FOPARA 2015. Lecture Notes in Computer Science(), vol 9964. Springer, Cham. https://doi.org/10.1007/978-3-319-46559-3_6
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