Closing the Performance Gap with Modern C++

  • Thomas HellerEmail author
  • Hartmut Kaiser
  • Patrick Diehl
  • Dietmar Fey
  • Marc Alexander Schweitzer
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9945)


On the way to Exascale, programmers face the increasing challenge of having to support multiple hardware architectures from the same code base. At the same time, portability of code and performance are increasingly difficult to achieve as hardware architectures are becoming more and more diverse. Today’s heterogeneous systems often include two or more completely distinct and incompatible hardware execution models, such as GPGPU’s, SIMD vector units, and general purpose cores which conventionally have to be programmed using separate tool chains representing non-overlapping programming models. The recent revival of interest in the industry and the wider community for the C++ language has spurred a remarkable amount of standardization proposals and technical specifications in the arena of concurrency and parallelism. This recently includes an increasing amount of discussion around the need for a uniform, higher-level abstraction and programming model for parallelism in the C++ standard targeting heterogeneous and distributed computing. Such an abstraction should perfectly blend with existing, already standardized language and library features, but should also be generic enough to support future hardware developments. In this paper, we present the results from developing such a higher-level programming abstraction for parallelism in C++ which aims at enabling code and performance portability over a wide range of architectures and for various types of parallelism. We present and compare performance data obtained from running the well-known STREAM benchmark ported to our higher level C++ abstraction with the corresponding results from running it natively. We show that our abstractions enable performance at least as good as the comparable base-line benchmarks while providing a uniform programming API on all compared target architectures.


Parallel Algorithm Hardware Architecture Memory Allocation Memory Placement High Level Interface 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This work is supported by the NSF awards 1240655 (STAR), 1447831 (PXFS), and 1339782 (STORM), and the DoE award DE-SC0008714 (XPRESS) and by the European Union’s Horizon 2020 research and innovation program under grant agreement No 671603.


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Copyright information

© Springer International Publishing AG 2016

Authors and Affiliations

  • Thomas Heller
    • 1
    • 5
    Email author
  • Hartmut Kaiser
    • 2
    • 5
  • Patrick Diehl
    • 3
    • 5
  • Dietmar Fey
    • 1
  • Marc Alexander Schweitzer
    • 3
    • 4
  1. 1.Computer Science 3, Computer ArchitecturesFriedrich-Alexander-UniversityErlangenGermany
  2. 2.Center for Computation and TechnologyLouisiana State UniversityBaton RougeUSA
  3. 3.Institute for Numerical SimulationUniversity of BonnBonnGermany
  4. 4.Meshfree Multiscale Methods, Fraunhofer SCAISchloss BirlinghovenSankt AugustinGermany
  5. 5.The STELLAR GroupBaton RougeUSA

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