Security Services for Mixed-Criticality Systems Based on Networked Multi-core Chips

  • Thomas KollerEmail author
  • Donatus Weber
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9923)


Modern cyber-physical systems are designed to execute safety-critical applications with different criticality levels on the same platform. Security is an emerging topic in this domain and gains more and more importance since security vulnerabilities in the systems are accompanied by the risk of malicious attacks. Targeting these vulnerabilities allows an attacker to manipulate the system which results in a decrease of dependability and safety. Therefore, security mechanisms are required to ensure an adequate protection against malicious attacks. The European FP7 project DREAMS introduces a service-based architecture to implement mixed-criticality systems on networked multi-core chips. The architecture is a cross-domain architecture and is based on core services for communication, execution, time synchronization and resource management. The security services extends these core services to provide secure communication, time synchronization and resource management for the architecture. This paper defines the required security properties to harden the DREAMS architecture against malicious attacks. The security properties are mapped to concrete security services that serve as basis for the implementation of the architecture. These services are categorized into different security levels and applied to the core services of the DREAMS architecture.


Mixed-criticality Security Service-based architecture Cyber-physical systems Embedded systems 



The research leading to these results has received funding from the European Union’s Seventh Framework Programme FP7 2007-2013 under grant agreement 610640.


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Chair for Data Communications SystemsUniversity of SiegenSiegenGermany
  2. 2.Chair for Embedded SystemsUniversity of SiegenSiegenGermany

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