Skip to main content
SpringerLink
Log in

Time-Interleaving

  • Chapter
  • First Online:
Analog-to-Digital Conversion

  • 5710 Accesses

Abstract

Time-interleaving allows to push the speed of the conversion to almost flash converter like values. The signal is split and processes a number of slower channels. The data stream is recombined in the digital domain. The problems associated with time-interleaving are the various errors that can occur: offsets, gain mismatches, sampling time differences, bandwidth variations, and for digital-to-analog conversion also reconstruction errors.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 69.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    PVT: process, voltage, and temperature deviations from nominal process specification.

Bibliography

  1. Dalt ND, Harteneck M, Sandner C, Wiesbauer A (2002) On the jit-ter requirements of the sampling clock for analog-to-digital converters. IEEE Trans Circuits Syst I 49:1354–1360

    Article  Google Scholar 

  2. Limotyrakis S, Kulchycki SD, Su DK, Wooley BA (2005) A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE J Solid-State Circuits 40:1057–1067

    Article  Google Scholar 

  3. van der Goes F, Ward CM, Astgimath S, Yan H, Riley J, Zeng Z, Mulder J, Wang S, Bult K (2014) A 1.5 mW 68 dB SNDR 80 Ms/s 2 interleaved pipelined SAR ADC in 28 nm CMOS. IEEE J Solid-State Circuits 49:2835–2845

    Article  Google Scholar 

  4. Bult K, Geelen GJGM (1990) A fast-settling CMOS op amp for SC circuits with 90-dB DC gain. IEEE J Solid-State Circuits 25:1379–1384

    Article  Google Scholar 

  5. Liu W, Chang y, Hsien S-K et al (2009) A 600 mW 30 mW 0.13 μm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. In: International solid-state circuits conference, digest of technical papers, pp 82-83

    Google Scholar 

  6. Snoeij MF, Theuwissen AJP, Makinwa KAA, Huijsing JH (2007) Multiple-ramp column-parallel ADC architectures for CMOS image sensors. IEEE J Solid-State Circuits 42:2986–2977

    Article  Google Scholar 

  7. Black WC, Hodges DA (1980) Time-interleaved converter arrays. IEEE J Solid-State Circuits 15(12):1022–1029

    Article  Google Scholar 

  8. Pelgrom MJM, Jochijms A, Heijns H (1987) A CCD delay line for video applications. IEEE Trans Consum Electron 33:603–609

    Article  Google Scholar 

  9. Kapusta R et al (2013) A 14-b 80 MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS. IEEE J Solid-State Circuits 48:3059–3066

    Article  Google Scholar 

  10. El-Chammas M, Murmann B (2011) A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration. IEEE J Solid-State Circuits 46(4):838–847

    Article  Google Scholar 

  11. Doris K, Janssen E, Nani C, Zanikopoulos A, Van der Wiede G (2011) A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. IEEE J Solid-State Circuits 46:2821–2833

    Article  Google Scholar 

  12. Kull L et al (2014) A 90-GS/s 8-b 667 mW 64x Interleaved SAR ADC in 32 nm Digital SOI CMOS. In: International solid-state circuits conference, digest of technical papers, pp 378–379

    Google Scholar 

  13. Kull L, Pliva J, Toifl T, Schmatz M, Francese PA, Menolfi C, Brändli M, Kossel M, Morf T, Meyer Andersen T, Leblebici Y (2016) Implementation of low-power 6–8 b 30–90 GS/s time-interleaved ADCs with optimized input bandwidth in 32 nm CMOS. IEEE J Solid-State Circuits 51:636–648

    Article  Google Scholar 

  14. Louwsma SM et al (2008) A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13μm CMOS. IEEE J Solid-State Circuits 43:778–786

    Article  Google Scholar 

  15. Varzaghani A et al (2013) A 10.3-GS/s, 6-bit flash ADC for 10G ethernet applications. IEEE J Solid-State Circuits 48(8):3038–3048

    Article  Google Scholar 

  16. Hsu C-C, Huang F-C, Shih C-Y, Huang C-C, Lin Y-H, Lee C-C, Razavi B (2007) An 11b 800MS/s time-interleaved ADC with digital background calibration. In: International solid-state circuits conference, digest of technical papers, pp 164–165

    Google Scholar 

  17. Janssen E et al (2013) An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS. In: International solid-state circuits conference, digest of technical papers, pp 464–465

    Google Scholar 

  18. Straayer M et al (2016) A 4GS/s time-interleaved RF ADC in 65nm CMOS with 4GHz input bandwidth. In: International solid-state circuits conference, digest of technical papers, pp 464–465

    Google Scholar 

  19. Ram’rez-Angulo J, Carvajal RG, Torralba A, Galán J, VegaLeal AP, Tombs J (2002) The flipped voltage follower: a useful cell for low-voltage low power circuit design. In: Proceedings ISCAS 2002, vol 3, pp 615–618

    Google Scholar 

  20. Kurosawa N, Kobayashi H, Maruyama K, Sugawara H, Kobayashi K (2001) Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans Circuits Syst I: Fundam Theory Appl 48:261–271

    Article  Google Scholar 

  21. Olieman E, Annema A-J, Nauta B (2015) An interleaved full Nyquist high-speed DAC technique. IEEE J Solid-State Circuits, 50:704–715

    Article  Google Scholar 

  22. Olieman E (2016) Time-interleaved high-speed D/A converters. Ph.D. thesis, University Twente

    Google Scholar 

  23. Wu J et al (2013) A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS. In: Symposium on VLSI circuits digest of technical papers, pp C92–93

    Google Scholar 

  24. Verbruggen B, Iriguchi M, Craninckx J (2012) A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. In: International solid-state circuits conference, digest of technical papers, pp 466–467

    Google Scholar 

  25. Brandolini M et al (2015) A 5 GS/s 150 mW 10 b SHA-less pipelined/SAR hybrid ADC for direct-sampling systems in 28 nm CMOS. IEEE J Solid-State Circuits 50:2922–2934

    Article  Google Scholar 

  26. Stepanovic D, Nikolic B (2013) A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS. IEEE J Solid-State Circuits 48:971–982

    Article  Google Scholar 

  27. Setterberg B et al (2013) A 14 b 2.5 GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction. In: International solid-state circuits conference, digest of technical papers, pp 466–467 10. Sigma-Delta Conversion

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. HELMOND, Noord-Brabant, The Netherlands

    Marcel Pelgrom

Authors
  1. Marcel Pelgrom
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Pelgrom, M. (2017). Time-Interleaving. In: Analog-to-Digital Conversion. Springer, Cham. https://doi.org/10.1007/978-3-319-44971-5_9

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-44971-5_9

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-44970-8

  • Online ISBN: 978-3-319-44971-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation