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Fundamentals and Failures in Die Preparation for 3D Packaging

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3D Microelectronic Packaging

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 57))

Abstract

Through-Silicon-Via (TSV) wafer processes have been reviewed by several authors previously, including temporary adhesive wafer bonding, high aspect ratio silicon etch, and wafer singulation. This chapter starts with a brief overview of TSV wafer fabrication and singulation processes. Then, it focuses on several key process issues which have not been discussed in previous review articles. The first process issue discussed in details here is the device wafer buckling or wrinkling postwafer thinning. This challenge might cause yield loss at the downstream lithography process. The fundamental mechanism behind this issue is investigated and several solutions are proposed. The second process discussed in details here is wafer debonding. Based on viscosity definition and wafer geometry, a closed-form analytical solution is proposed for the thermal sliding wafer debonding process, which can be used for process control and throughput optimization. The next two processes discussed are laser scribe and saw dicing, which impact die edge chipping and low-k inter layer dielectric (ILD) delamination. A closed-form solution of chipping induced by saw dicing is also investigated. The last process discussed in this chapter is the challenges and solution options for die pick and place.

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Acknowledgments

The authors would like to acknowledge Dr. Sairam Agraharam of Intel Corp. for valuable discussions. The editors would like to thank Guotao Wang of Intel Corp. for his critical review of this Chapter.

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  1. Intel Corporation, 5000 W. Chandler Blvd, Chandler, AZ, 85226, USA

    Hualiang Shi & Erasenthiran Poonjolai

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  1. Hualiang Shi
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Correspondence to Hualiang Shi .

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  1. Intel Corporation, Chandler, Arizona, USA

    Yan Li

  2. Intel Corporation, Chandler, Arizona, USA

    Deepak Goyal

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Shi, H., Poonjolai, E. (2017). Fundamentals and Failures in Die Preparation for 3D Packaging. In: Li, Y., Goyal, D. (eds) 3D Microelectronic Packaging. Springer Series in Advanced Microelectronics, vol 57. Springer, Cham. https://doi.org/10.1007/978-3-319-44586-1_5

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  • DOI: https://doi.org/10.1007/978-3-319-44586-1_5

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