Abstract
In this chapter, we focus on a novel two-level logic representation. We define Majority Normal Form (MNF), as an alternative to the traditional Disjunctive Normal Form (DNF) and the Conjunctive Normal Form (CNF). After a brief investigation on the MNF expressive power, we study the problem of MNF-SATisfiability (MNF-SAT). We prove that MNF-SAT is NP-complete, as its CNF-SAT counterpart. However, we show practical restrictions on MNF formula whose satisfiability can be decided in polynomial time. We finally propose a simple algorithm to solve MNF-SAT, based on the intrinsic functionality of two-level majority logic. Although an automated MNF-SAT solver is still under construction, manual examples already demonstrate promising opportunities.
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Notes
- 1.
The tautology check problem has been introduced in Chap. 4 of this book.
- 2.
The final majority operator in an MNF is the one in the top layer of the two-level representation form, thus computing the output MNF function.
References
L. Amaru, P.-E. Gaillardon, G. De Micheli, BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition, in Proceedings of the DAC (2013)
L. Amaru, P.-E. Gaillardon, G. De Micheli, Majority inverter graphs, in Proceedings of the DAC (2014)
G. Yang, W.N.N. Hung, X. Song, M. Perkowski, Majority-based reversible logic gates. Theor. Comput. Sci. 334, 259–274 (2005)
H. Pospesel, Introduction to Logic: Propositional Logic (Pearson, New York, 1999)
T. Sasao, Switching Theory for Logic Synthesis (Springer, Heidelberg, 1999)
S. Cook, The complexity of theorem-proving procedures, in Proceedings of ACM Symposium on Theory of Computing (1971)
A. Biere, M. Heule, H. van Maaren, T. Walsh, Handbook of Satisfiability (IOS Press, Amsterdam, 2009)
K.J. Chen et al., InP-based high-performance logic elements using resonant-tunneling devices. IEEE Electr. Dev. Lett. 17(3), 127–129 (1996)
M. Krause, P. Pudlak, On the computational power of depth-2 circuits with threshold and modulo gates. Theor. Comput. Sci. 174, 137–156 (1997)
A.A. Sherstov, Separating AC 0 from depth-2 majority circuits, Proceedings of the STOC (2007)
N. Een, N. Sorensson, MiniSat - A SAT Solver with Conflict-Clause Minimization, SAT (2005)
N. Een, A. Mishchenko, N. Sorensson, Applying Logic Synthesis for Speeding Up SAT, SAT (2007)
R.E. Bryant, Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C–35, 677–691 (1986)
M.R. Garey, D.S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness (W. H. Freeman, San Francisco, 1979)
H.R. Lewis, Satisfiability problems for propositional calculi. Math. Syst. Theory 13, 45–53 (1979)
R. Impagliazzo, A Satisfiability Algorithm for Sparse Depth Two Threshold Circuits, Arxiv (2013)
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Amaru, L.G. (2017). Majority Normal Form Representation and Satisfiability. In: New Data Structures and Algorithms for Logic Synthesis and Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-43174-1_5
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DOI: https://doi.org/10.1007/978-3-319-43174-1_5
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