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Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management pp 89–104Cite as

Blocker and Clock-Jitter Performance in CT ΣΔ ADCs for Consumer Radio Receivers

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Abstract

The smallest, most efficient CT ΣΔ ADCs have typically been feed‐forward (FF) compensated single-bit implementations. However, this has not translated in consumer radio receivers because of poor performance in the presence of out‐of‐band near-blockers and clock jitter. As a result SAR ADCs, filtering, and multi-bit CT ΣΔ ADCs have become increasingly prevalent at the cost of receiver power and area. This paper presents the challenges and design techniques used to restore single-bit FF CT ΣΔ ADC performance and efficiency in the context of a modern consumer radio receiver.

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Authors and Affiliations

  1. Broadcom Limited, Sydney, NSW, Australia

    Sebastián Loeda

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  1. Sebastián Loeda
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Correspondence to Sebastián Loeda .

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Editors and Affiliations

  1. Department of Physics “ G. Occhialini, University of Milan, MILANO, Milano, Italy

    Andrea Baschirotto

  2. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

    Pieter Harpe

  3. Electronic Instrumentation Laboratory, Delft University of Technology, Delft , The Netherlands

    Kofi A. A. Makinwa

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Loeda, S. (2017). Blocker and Clock-Jitter Performance in CT ΣΔ ADCs for Consumer Radio Receivers. In: Baschirotto, A., Harpe, P., Makinwa, K. (eds) Wideband Continuous-time ΣΔ ADCs, Automotive Electronics, and Power Management. Springer, Cham. https://doi.org/10.1007/978-3-319-41670-0_5

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  • DOI: https://doi.org/10.1007/978-3-319-41670-0_5

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-41669-4

  • Online ISBN: 978-3-319-41670-0

  • eBook Packages: EngineeringEngineering (R0)

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