Advertisement

Structural Synthesis for GXW Specifications

  • Chih-Hong ChengEmail author
  • Yassine Hamza
  • Harald Ruess
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9779)

Abstract

We define the \(\textsf {\small {GXW}} \) fragment of linear temporal logic (LTL) as the basis for synthesizing embedded control software for safety-critical applications. Since \(\textsf {\small {GXW}} \) includes the use of a weak-until operator we are able to specify a number of diverse programmable logic control (PLC) problems, which we have compiled from industrial training sets. For \(\textsf {\small {GXW}} \) controller specifications, we develop a novel approach for synthesizing a set of synchronously communicating actor-based controllers. This synthesis algorithm proceeds by means of recursing over the structure of \(\textsf {\small {GXW}} \) specifications, and generates a set of dedicated and synchronously communicating sub-controllers according to the formula structure. In a subsequent step, 2QBF constraint solving identifies and tries to resolve potential conflicts between individual \(\textsf {\small {GXW}} \) specifications. This structural approach to \(\textsf {\small {GXW}} \) synthesis supports traceability between requirements and the generated control code as mandated by certification regimes for safety-critical software. Our experimental results suggest that GXW synthesis scales well to industrial-sized control synthesis problems with 20 input and output ports and beyond.

Keywords

Output Port Input Port Linear Temporal Logic Disjunctive Normal Form Programmable Logic Control 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgement

We thank Lacramioara Aştefănoaei for her fruitful feedback during the development of the paper, and CAV reviewers for their constructive comments. This work is supported by the H2020 project openMOS, GA no. 680735.

References

  1. 1.
    Full version available at http://arxiv.org/abs/1605.01153
  2. 2.
    Online training material for PLC programming. http://plc-scada-dcs.blogspot.com/
  3. 3.
    CODESYS - industrial IEC 61131–3 programming framework. http://www.codesys.com/
  4. 4.
  5. 5.
    Bloem, R., Cimatti, A., Greimel, K., Hofferek, G., Könighofer, R., Roveri, M., Schuppan, V., Seeber, R.: RATSY – a new requirements analysis tool with synthesis. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 425–429. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  6. 6.
    Bloem, R., Ehlers, R., Jacobs, S., Knighofer, R.: How to handle assumptions in synthesis. In: SYNT, pp. 34–50 (2014). EPTCS 157Google Scholar
  7. 7.
    Bloem, R., Könighofer, B., Könighofer, R., Wang, C.: Shield synthesis: runtime enforcement for reactive systems. In: Baier, C., Tinelli, C. (eds.) TACAS 2015. LNCS, vol. 9035, pp. 533–548. Springer, Heidelberg (2015)Google Scholar
  8. 8.
    Bohy, A., Bruyère, V., Filiot, E., Jin, N., Raskin, J.-F.: Acacia+, a tool for LTL synthesis. In: Madhusudan, P., Seshia, S.A. (eds.) CAV 2012. LNCS, vol. 7358, pp. 652–657. Springer, Heidelberg (2012)CrossRefGoogle Scholar
  9. 9.
    Brenguier, R., Prez, G.A., Raskin, J.-F., Sankur, O.: AbsSynthe: abstract synthesis from succinct safety specifications. In: SYNT, pp. 100–116 (2014). EPTCS 157Google Scholar
  10. 10.
    Cheng, C.-H., Huang, C.-H., Ruess, H., Stattelmann, S.: \({{\sf G4LTL-ST}}\): automatic generation of PLC programs. In: Biere, A., Bloem, R. (eds.) CAV 2014. LNCS, vol. 8559, pp. 541–549. Springer, Heidelberg (2014)Google Scholar
  11. 11.
    Ehlers, R.: Unbeast: symbolic bounded synthesis. In: Abdulla, P.A., Leino, K.R.M. (eds.) TACAS 2011. LNCS, vol. 6605, pp. 272–275. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  12. 12.
    Eker, J., Janneck, J., Lee, E.A., Liu, J., Liu, X., Ludvig, J., Sachs, S., Xiong, Y.: Taming heterogeneity - the Ptolemy approach. Proc. IEEE 91(1), 127–144 (2003)CrossRefGoogle Scholar
  13. 13.
    Jacobs, S., Bloem, R., Brenguier, R., Ehlers, R., Hell, T., Knighofer, R. Prez, G.A., Raskin, J.-F., Ryzhyk, L., Sankur, O., Seidl, M., Tentrup, L., Walker, A.: The first reactive synthesis competition. In: SYNTCOMP 2014 (2014). http://arxiv.org/abs/1506.08726
  14. 14.
    Jobstmann, B., Bloem, R.: Optimizations for LTL synthesis. In: FMCAD, pp. 117–124. IEEE (2006)Google Scholar
  15. 15.
    Jobstmann, B., Galler, S., Weiglhofer, M., Bloem, R.: Anzu: a tool for property synthesis. In: Damm, W., Hermanns, H. (eds.) CAV 2007. LNCS, vol. 4590, pp. 258–262. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  16. 16.
    Kaftan, J.: Praktische Beispiele mit AC500 von ABB: 45 Aufgaben und Lsungen mit CoDeSys (2014). http://pwww.kaftan-media.com/. ISBN 978-3-943211-05-4
  17. 17.
    Knighofer, R., Seidl, M.: Demiurge 1.2: A SAT-Based Synthesis Tool. Tool description for the SyntComp 2015 competition. http://www.iaik.tugraz.at/content/research/opensource/demiurge/
  18. 18.
    Lee, E.A., Messerschmitt, D.G.: Static scheduling of synchronous data flow programs for digital signal processing. IEEE Trans. Comput. 36(1), 24–35 (1987)CrossRefGoogle Scholar
  19. 19.
    Lee, E.A., Messerschmitt, D.G.: Synchronous data flow. Proc. IEEE 75(9), 1235–1245 (1987)CrossRefGoogle Scholar
  20. 20.
    Li, W.-C.: Specification mining: new formalisms, algorithms and applications. Ph.D. thesis. UC Berkeley (2015)Google Scholar
  21. 21.
    Lonsing, F., Biere, A.: DepQBF: a dependency-aware QBF solver. J. Satisfiability Boolean Model. Comput. 7, 71–76 (2010)Google Scholar
  22. 22.
    Lustig, Y., Vardi, M.Y.: Synthesis from component libraries. STTT 15(5–6), 603–618 (2013)CrossRefzbMATHGoogle Scholar
  23. 23.
    Mavin, A., Wilkinson, P., Harwood, A., Novak, M.: Easy Approach to Requirements Syntax (EARS). In: RE, pp. 317–322. IEEE (2009)Google Scholar
  24. 24.
    Petry, J.: IEC 61131–3 mit CoDeSys V3: Ein Praxisbuch fuer SPS-Programmierer. Eigenverlag 3S-Smart Software Solutions. ISBN 978-3-000465-08-6 (2011)Google Scholar
  25. 25.
    Piterman, N., Pnueli, A., Sa’ar, Y.: Synthesis of reactive(1) designs. In: Emerson, E.A., Namjoshi, K.S. (eds.) VMCAI 2006. LNCS, vol. 3855, pp. 364–380. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  26. 26.
    Pnueli, A.: The temporal logic of programs. In: FOCS, pp. 46–57. IEEE (1977)Google Scholar
  27. 27.
    Pnueli, A., Rosner, R.: On the synthesis of a reactive module. In: POPL, pp. 179–190. IEEE (1989)Google Scholar
  28. 28.
    Schewe, S., Finkbeiner, B.: Bounded synthesis. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds.) ATVA 2007. LNCS, vol. 4762, pp. 474–488. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  29. 29.
    Tarjan, R.E.: Depth-first search and linear graph algorithms. SIAM J. Comput. 1(2), 146–160 (1972)MathSciNetCrossRefzbMATHGoogle Scholar
  30. 30.
    Tripakis, S., Bui, D., Geilen, M., Rodiers, B., Lee, E.A.: Compositionality in synchronous data flow: modular code generation from hierarchical SDF graphs. ACM Trans. Embed. Comput. Syst. 12(3), 83:1–83:26 (2013). http://doi.acm.org/10.1145/2442116.2442133, articleno 83, ISSN = 1539-9087CrossRefGoogle Scholar
  31. 31.
    Wong, K.-W., Ehlers, R., Kress-Gazit, H.: Correct high-level robot behavior in environments with unexpected events. In: Robotics: Science and Systems X (RSS X) (2014)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.fortiss - An-Institut Technische Universität MünchenMunichGermany

Personalised recommendations