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RNS in Cryptography

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Residue Number Systems

Abstract

In cryptographic applications such as RSA encryption, Diffie-Hellman Key exchange, Elliptic curve cryptography, etc., modulo multiplication and modulo exponentiation of large numbers, of bit lengths varying between 160 bits to 2048 bits, typically will be required. Two popular techniques are based on Barrett reduction and Montgomery multiplication. However, to perform the operation (X Y) mod N for a single modulus, RNS using several small word lengths moduli can be employed. This topic has received recently considerable attention. We deal with both RNS-based and non-RNS based (i.e. using only one modulus) implementations in the following sections. In this chapter, we also consider applications of RNS in Elliptic Curve Cryptography processors and for implementation of Pairing protocols.

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References

  1. W. Stallings, Cryptography and Network Security, Principles and Practices, 6th edn. (Pearson, Upper Saddle River, 2013)

    Google Scholar 

  2. B. Schneier, Applied Cryptography: Protocols, Algorithms, and Source Code in C (Wiley, New York, 1996)

    MATH  Google Scholar 

  3. P. Barrett, Implementing the Rivest-Shamir-Adleman Public Key algorithm on a standard Digital Signal Processor, in Proceedings of Annual Cryptology Conference on Advances in Cryptology, (CRYPTO‘86), pp. 311–323 (1986)

    Google Scholar 

  4. A. Menezes, P. van Oorschot, S. Vanstone, Handbook of Applied Cryptography (CRC, Boca Raton, 1996)

    Book  MATH  Google Scholar 

  5. J.-F. Dhem, Modified version of the Barrett Algorithm, Technical report (1994)

    Google Scholar 

  6. M. Knezevic, F. Vercauteren, I. Verbauwhede, Faster interleaved modular multiplication based on Barrett and Montgomery reduction methods. IEEE Trans. Comput. 59, 1715–1721 (2010)

    Article  MathSciNet  Google Scholar 

  7. J.-J. Quisquater, Encoding system according to the so-called RSA method by means of a microcontroller and arrangement implementing the system, US Patent #5,166,978, 24 Nov 1992

    Google Scholar 

  8. C.D. Walter, Fast modular multiplication by operand scanning, Advances in Cryptology, LNCS, vol. 576 (Springer, 1991), pp. 313–323

    Google Scholar 

  9. E.F. Brickell, A fast modular multiplication algorithm with application to two key cryptography, Advances in Cryptology Proceedings of Crypto 82 (Plenum Press, New York, 1982), pp. 51–60

    Google Scholar 

  10. C.K. Koc. RSA Hardware Implementation. TR 801, RSA Laboratories, (April 1996)

    Google Scholar 

  11. C.K. Koc, T. Acar, B.S. Kaliski Jr., Analyzing and comparing Montgomery Multiplication Algorithms, in IEEE Micro, pp. 26–33 (1996)

    Google Scholar 

  12. M. McLoone, C. McIvor, J.V. McCanny, Coarsely integrated Operand Scanning (CIOS) architecture for high-speed Montgomery modular multiplication, in IEEE International Conference on Field Programmable Technology (ICFPT), pp. 185–192 (2004)

    Google Scholar 

  13. M. McLoone, C. McIvor, J.V. McCanny, Montgomery modular multiplication architecture for public key cryptosystems, in IEEE Workshop on Signal Processing Systems (SIPS), pp. 349–354 (2004)

    Google Scholar 

  14. C.D. Walter, Montgomery exponentiation needs no final subtractions. Electron. Lett. 35, 1831–1832 (1999)

    Article  Google Scholar 

  15. H. Orup, Simplifying quotient determination in high-radix modular multiplication, in Proceedings of IEEE Symposium on Computer Arithmetic, pp. 193–199 (1995)

    Google Scholar 

  16. C. McIvor, M. McLoone, J.V. McCanny, Modified Montgomery modular multiplication and RSA exponentiation techniques, in Proceedings of IEE Computers and Digital Techniques, vol. 151, pp. 402–408 (2004)

    Google Scholar 

  17. N. Nedjah, L.M. Mourelle, Three hardware architectures for the binary modular exponentiation: sequential, parallel and systolic. IEEE Trans. Circuits Syst. I 53, 627–633 (2006)

    Article  MathSciNet  Google Scholar 

  18. M.D. Shieh, J.H. Chen, W.C. Lin, H.H. Wu, A new algorithm for high-speed modular multiplication design. IEEE Trans. Circuits Syst. I 56, 2009–2019 (2009)

    Article  MathSciNet  Google Scholar 

  19. C.C. Yang, T.S. Chang, C.W. Jen, A new RSA cryptosystem hardware design based on Montgomery’s algorithm. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 45, 908–913 (1998)

    Article  MATH  Google Scholar 

  20. A. Tenca, C. Koc, A scalable architecture for modular multiplication based on Montgomery’s algorithm. IEEE Trans. Comput. 52, 1215–1221 (2003)

    Article  Google Scholar 

  21. D. Harris, R. Krishnamurthy, M. Anders, S. Mathew, S. Hsu, An improved unified scalable radix-2 Montgomery multiplier, in IEEE Symposium on Computer Arithmetic, pp. 172–175 (2005)

    Google Scholar 

  22. K. Kelly, D. Harris, Very high radix scalable Montgomery multipliers, in Proceedings of International Workshop on System-on-Chip for Real-Time Applications, pp. 400–404 (2005)

    Google Scholar 

  23. N. Jiang, D. Harris, Parallelized Radix-2 scalable Montgomery multiplier, in Proceedings of IFIP International Conference on Very Large-Scale Integration (VLSI-SoC 2007), pp. 146–150 (2007)

    Google Scholar 

  24. N. Pinckney, D. Harris, Parallelized radix-4 scalable Montgomery multipliers. J. Integr. Circuits Syst. 3, 39–45 (2008)

    Google Scholar 

  25. K. Kelly, D. Harris, Parallelized very high radix scalable Montgomery multipliers, in Proceedings of Asilomar Conference on Signals, Systems and Computers, pp. 1196–1200 (2005)

    Google Scholar 

  26. M. Huang, K. Gaj, T. El-Ghazawi, New hardware architectures for Montgomery modular multiplication algorithm. IEEE Trans. Comput. 60, 923–936 (2011)

    Article  MathSciNet  Google Scholar 

  27. M.D. Shieh, W.C. Lin, Word-based Montgomery modular multiplication algorithm for low-latency scalable architectures. IEEE Trans. Comput. 59, 1145–1151 (2010)

    Article  MathSciNet  Google Scholar 

  28. A. Miyamoto, N. Homma, T. Aoki, A. Satoh, Systematic design of RSA processors based on high-radix Montgomery multipliers. IEEE Trans. VLSI Syst. 19, 1136–1146 (2011)

    Article  Google Scholar 

  29. K.C. Posch, R. Posch, Modulo reduction in residue Number Systems. IEEE Trans. Parallel Distrib. Syst. 6, 449–454 (1995)

    Article  MATH  Google Scholar 

  30. C. Bajard, L.S. Didier, P. Kornerup, An RNS Montgomery modular multiplication Algorithm. IEEE Trans. Comput. 47, 766–776 (1998)

    Article  MathSciNet  Google Scholar 

  31. J.C. Bajard, L. Imbert, A full RNS implementation of RSA. IEEE Trans. Comput. 53, 769–774 (2004)

    Article  Google Scholar 

  32. A.P. Shenoy, R. Kumaresan, Fast base extension using a redundant modulus in RNS. IEEE Trans. Comput. 38, 293–297 (1989)

    Article  MATH  Google Scholar 

  33. H. Nozaki, M. Motoyama, A. Shimbo, S. Kawamura, Implementation of RSA Algorithm Based on RNS Montgomery Multiplication, in Cryptographic Hardware and Embedded Systems—CHES, ed. by C. Paar (Springer, Berlin, 2001), pp. 364–376

    Google Scholar 

  34. S. Kawamura, M. Koike, F. Sano, A. Shimbo, Cox-Rower architecture for fast parallel Montgomery multiplication, in Proceedings of International Conference on Theory and Application of Cryptographic Techniques: Advances in Cryptology, (EUROCRYPT 2000), pp. 523–538 (2000)

    Google Scholar 

  35. F. Gandino, F. Lamberti, G. Paravati, J.C. Bajard, P. Montuschi, An algorithmic and architectural study on Montgomery exponentiation in RNS. IEEE Trans. Comput. 61, 1071–1083 (2012)

    Article  MathSciNet  Google Scholar 

  36. D. Schinianakis, T. Stouraitis, A RNS Montgomery multiplication architecture, in Proceedings of ISCAS, pp. 1167–1170 (2011)

    Google Scholar 

  37. Y.T. Jie, D.J. Bin, Y.X. Hui, Z.Q. Jin, An improved RNS Montgomery modular multiplier, in Proceedings of the International Conference on Computer Application and System Modeling (ICCASM 2010), pp. V10-144–147 (2010)

    Google Scholar 

  38. D. Schinianakis, T. Stouraitis, Multifunction residue architectures for cryptography. IEEE Trans. Circuits Syst. 61, 1156–1169 (2014)

    Article  Google Scholar 

  39. H.M. Yassine, W.R. Moore, Improved mixed radix conversion for residue number system architectures, in Proceedings of IEE Part G, vol. 138, pp. 120–124 (1991)

    Google Scholar 

  40. M. Ciet, M. Neve, E. Peeters, J.J. Quisquater, Parallel FPGA implementation of RSA with residue number systems—can side-channel threats be avoided?, in 46th IEEE International MW Symposium on Circuits and Systems, vol. 2, pp. 806–810 (2003)

    Google Scholar 

  41. J.-J. Quisquater, C. Couvreur, Fast decipherment algorithm for RSA public key cryptosystem. Electron. Lett. 18, 905–907 (1982)

    Article  Google Scholar 

  42. R. Szerwinski, T. Guneysu, Exploiting the power of GPUs for Asymmetric Cryptography. Lect. Notes Comput. Sci. 5154, 79–99 (2008)

    Article  MATH  Google Scholar 

  43. B.S. Kaliski Jr., The Montgomery inverse and its applications. IEEE Trans. Comput. 44, 1064–1065 (1995)

    Article  MATH  Google Scholar 

  44. E. Savas, C.K. Koc, The Montgomery modular inverse—revisited. IEEE Trans. Comput. 49, 763–766 (2000)

    Article  MathSciNet  Google Scholar 

  45. A.A.A. Gutub, A.F. Tenca, C.K. Koc, Scalable VLSI architecture for GF(p) Montgomery modular inverse computation, in IEEE Computer Society Annual Symposium on VLSI, pp. 53–58 (2002)

    Google Scholar 

  46. E. Savas, A carry-free architecture for Montgomery inversion. IEEE Trans. Comput. 54, 1508–1518 (2005)

    Article  Google Scholar 

  47. J. Bucek, R. Lorencz, Comparing subtraction free and traditional AMI, in Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, pp. 95–97 (2006)

    Google Scholar 

  48. D.M. Schinianakis, A.P. Kakarountas, T. Stouraitis, A new approach to elliptic curve cryptography: an RNS architecture, in IEEE MELECON, Benalmádena (Málaga), Spain, pp. 1241–1245, 16–19 May 2006

    Google Scholar 

  49. D.M. Schinianakis, A.P. Fournaris, H.E. Michail, A.P. Kakarountas, T. Stouraitis, An RNS implementation of an F p elliptic curve point multiplier. IEEE Trans. Circuits Syst. I Reg. Pap. 56, 1202–1213 (2009)

    Article  MathSciNet  Google Scholar 

  50. M. Esmaeildoust, D. Schnianakis, H. Javashi, T. Stouraitis, K. Navi, Efficient RNS implementation of Elliptic curve point multiplication over GF(p). IEEE Trans. Very Large Scale Integration (VLSI) Syst. 21, 1545–1549 (2013)

    Article  Google Scholar 

  51. P.V. Ananda Mohan, RNS to binary converter for a new three moduli set {2n+1 -1, 2n, 2n-1}. IEEE Trans. Circuits Syst. II 54, 775–779 (2007)

    Article  MathSciNet  Google Scholar 

  52. M. Esmaeildoust, K. Navi, M. Taheri, A.S. Molahosseini, S. Khodambashi, Efficient RNS to Binary Converters for the new 4- moduli set {2n, 2n+1 -1, 2n-1, 2n-1 -1}”. IEICE Electron. Exp. 9(1), 1–7 (2012)

    Article  Google Scholar 

  53. J.C. Bajard, S. Duquesne, M. Ercegovac, Combining leak resistant arithmetic for elliptic curves defined over Fp and RNS representation, Cryptology Reprint Archive 311 (2010)

    Google Scholar 

  54. M. Joye, J.J. Quisquater, Hessian elliptic curves and side channel attacks. CHES, LNCS 2162, 402–410 (2001)

    MathSciNet  MATH  Google Scholar 

  55. P.Y. Liardet, N. Smart, Preventing SPA/DPA in ECC systems using Jacobi form. CHES, LNCS 2162, 391–401 (2001)

    MathSciNet  MATH  Google Scholar 

  56. E. Brier, M. Joye, Wierstrass elliptic curves and side channel attacks. Public Key Cryptography LNCS 2274, 335–345 (2002)

    Article  MATH  Google Scholar 

  57. P.L. Montgomery, Speeding the Pollard and elliptic curve methods of factorization. Math. Comput. 48, 243–264 (1987)

    Article  MathSciNet  MATH  Google Scholar 

  58. A. Joux, A one round protocol for tri-partite Diffie-Hellman, Algorithmic Number Theory, LNCS, pp. 385–394 (2000)

    Google Scholar 

  59. D. Boneh, M.K. Franklin, Identity based encryption from the Weil Pairing, in Crypto 2001, LNCS, vol. 2139, pp. 213–229 (2001)

    Google Scholar 

  60. D. Boneh, B. Lynn, H. Shachm, Short signatures for the Weil pairing. J. Cryptol. 17, 297–319 (2004)

    Article  MathSciNet  MATH  Google Scholar 

  61. J. Groth, A. Sahai, Efficient non-interactive proof systems for bilinear groups, in 27th Annual International Conference on Advances in Cryptology, Eurocrypt 2008, pp. 415–432 (2008)

    Google Scholar 

  62. V.S. Miller, The Weil pairing and its efficient calculation. J. Cryptol. 17, 235–261 (2004)

    Article  MathSciNet  MATH  Google Scholar 

  63. P.S.L.M. Barreto, H.Y. Kim, B. Lynn, M. Scott, Efficient algorithms for pairing based cryptosystems, in Crypto 2002, LCNS 2442, pp. 354–369 (Springer, Berlin, 2002)

    Google Scholar 

  64. F. Hess, N.P. Smart, F. Vercauteren, The eta paring revisited. IEEE Trans. Inf. Theory 52, 4595–4602 (2006)

    Article  MathSciNet  MATH  Google Scholar 

  65. F. Lee, H.S. Lee, C.M. Park, Efficient and generalized pairing computation on abelian varieties, Cryptology ePrint Archive, Report 2008/040 (2008)

    Google Scholar 

  66. F. Vercauteren, Optimal pairings. IEEE Trans. Inf. Theory 56, 455–461 (2010)

    Article  MathSciNet  Google Scholar 

  67. S. Duquesne, N. Guillermin, A FPGA pairing implementation using the residue number System, in Cryptology ePrint Archive, Report 2011/176(2011), http://eprint.iacr.org/

  68. S. Duquesne, RNS arithmetic in Fp k and application to fast pairing computation, Cryptology ePrint Archive, Report 2010/55 (2010), http://eprint.iacr.org

  69. P. Barreto, M. Naehrig, Pairing friendly elliptic curves of prime order, SAC, 2005. LNCS 3897, 319–331 (2005)

    MathSciNet  MATH  Google Scholar 

  70. A. Miyaji, M. Nakabayashi, S. Takano, New explicit conditions of elliptic curve traces for FR-reduction. IEICE Trans. Fundam. 84, 1234–1243 (2001)

    MATH  Google Scholar 

  71. B. Lynn, On the implementation of pairing based cryptography, Ph.D. Thesis PBC Library, https://crypto.stanford.edu/~blynn/

  72. C. Costello, Pairing for Beginners, www.craigcostello.com.au/pairings/PairingsForBeginners.pdf

  73. J.C. Bazard, M. Kaihara, T. Plantard, Selected RNS bases for modular multiplication, in 19th IEEE International Symposium on Computer Arithmetic, pp. 25–32 (2009)

    Google Scholar 

  74. A. Karatsuba, The complexity of computations, in Proceedings of Staklov Institute of Mathematics, vol. 211, pp. 169–183 (1995)

    Google Scholar 

  75. P.L. Montgomery, Five-, six- and seven term Karatsuba like formulae. IEEE Trans. Comput. 54, 362–369 (2005)

    Article  MATH  Google Scholar 

  76. J. Fan, F. Vercauteren, I. Verbauwhede, Efficient hardware implementation of Fp-arithmetic for pairing-friendly curves. IEEE Trans. Comput. 61, 676–685 (2012)

    Article  MathSciNet  Google Scholar 

  77. J. Fan, F. Vercauteren, I. Verbauwhede, Faster Fp-Arithmetic for cryptographic pairings on Barreto Naehrig curves, in CHES, vol. 5747, LNCS, pp. 240–253 (2009)

    Google Scholar 

  78. J. Fan, http://www.iacr.org/workshops/ches/ches2009/presentations/08_Session_5/CHES2009_fan_1.pdf

  79. J. Chung, M.A. Hasan, Low-weight polynomial form integers for efficient modular multiplication. IEEE Trans. Comput. 56, 44–57 (2007)

    Article  MathSciNet  Google Scholar 

  80. J. Chung, M. Hasan, Montgomery reduction algorithm for modular multiplication using low weight polynomial form integers, in IEEE 18th Symposium on Computer Arithmetic, pp. 230–239 (2007)

    Google Scholar 

  81. C.C. Corona, E.F. Moreno, F.R. Henriquez, Hardware design of a 256-bit prime field multiplier for computing bilinear pairings, in 2011 International Conference on Reconfigurable Computing and FPGAs, pp. 229–234 (2011)

    Google Scholar 

  82. S. Srinath, K. Compton, Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks, in Proceedings of 18th Annual ACM/Sigda International Symposium on Field Programmable Gate Arrays, FPGA ‘10, New York, pp. 51–58 (2010)

    Google Scholar 

  83. R. Brinci, W. Khmiri, M. Mbarek, A.B. Rabaa, A. Bouallegue, F. Chekir, Efficient multipliers for pairing over Barreto-Naehrig curves on Virtex -6 FPGA, iacr Cryptology Eprint Archive (2013)

    Google Scholar 

  84. A.J. Devegili, C. OhEigertaigh, M. Scott, R. Dahab, Multiplication and squaring on pairing friendly fields, in Cryptology ePrint Archive, vol. 71 (2006)

    Google Scholar 

  85. A.L. Toom, The complexity of a scheme of functional elements realizing the multiplication of integers. Sov. Math. 4, 714–716 (1963)

    MATH  Google Scholar 

  86. S.A. Cook, On the minimum computation time of functions, Ph.D. Thesis, Harvard University, Department of Mathematics, 1966

    Google Scholar 

  87. J. Chung, M.A. Hasan, Asymmetric squaring formulae, Technical Report, CACR 2006-24, University of Waterloo (2006), http://www.cacr.uwaterloo.ca/techreports/2006/cacr2006-24.pdf

  88. D. Hankerson, A. Menezes, M. Scott, Software Implementation of Pairings, in Identity Based Cryptography, Chapter 12, ed. by M. Joye, G. Neven (IOS Press, Amsterdam, 2008), pp. 188–206

    Google Scholar 

  89. G.X. Yao, J. Fan, R.C.C. Cheung, I. Verbauwhede, A high speed pairing Co-processor using RNS and lazy reduction, eprint.iacr.org/2011/258.pdf

    Google Scholar 

  90. M. Scott, Implementing Cryptographic Pairings, ed. by T. Takagi, T. Okamoto, E. Okamoto, T. Okamoto, Pairing Based Cryptography, Pairing 2007, LNCS, vol. 4575, pp. 117–196 (2007)

    Google Scholar 

  91. J.L. Beuchat, J.E. Gonzalez-Diaz, S. Mitsunari, E. Okamoto, F. Rodriguez-Henriquez, T. Terya, in High Speed Software Implementation of the Optimal Ate Pairing over Barreto-Naehrig Curves, ed. by M. Joye, A. Miyaji, A. Otsuka, Pairing 2010, LNCS 6487, pp. 21–39 (2010)

    Google Scholar 

  92. M. Scott, N. Benger, M. Charlemagne, L.J.D. Perez, E.J. Kachisa, On the final exponentiation for calculating pairings on ordinary elliptic curves, Cryptology ePrint Archive, Report 2008/490(2008), http://eprint.iacr.org/2008/490.pdf

  93. A.J. Devegili, M. Scott, R. Dahab, Implementing cryptographic pairings over Barreto-Naehrig curves, Pairing 2007, vol. 4575 LCNS (Springer, Berlin, 2007), pp. 197–207

    Google Scholar 

  94. J. Olivos, On vectorial addition chains. J. Algorithm 2, 13–21 (1981)

    Article  MathSciNet  MATH  Google Scholar 

  95. G.X. Yao, J. Fn, R.C.C. Cheung, I. Verbauwhede, Novel RNS parameter selection for fast modular multiplication. IEEE Trans. Comput. 63, 2099–2105 (2014)

    Article  MathSciNet  Google Scholar 

  96. C. Costello, T. Lange, M. Naehrig, Faster pairing computations on curves with high degree twists, ed. by P. Nguyen, D. Pointcheval, PKC 2010, LNCS, vol. 6056, pp. 224–242 (2010)

    Google Scholar 

  97. D. Aranha, K. Karabina, P. Longa, C.H. Gebotys, J. Lopez, Faster explicit formulae for computing pairings over ordinary curves, Cryptology ePrint Archive, Report 2010/311 (2010), http://eprint.iacr.org/

  98. R. Granger, M. Scott, Faster squaring in the cyclotomic subgroups of sixth degree extensions, PKC-2010, 6056, pp. 209–223 (2010)

    Google Scholar 

  99. N. Guillermin, A high speed coprocessor for elliptic curve scalar multiplications over Fp, CHES, LNCS (2010)

    Google Scholar 

  100. D. Kammler, D. Zhang, P. Schwabe, H. Scharwaechter, M. Langenberg, D. Auras, G. Ascheid, R. Leupers, R. Mathar, H. Meyr, Designing an ASIP for cryptographic pairings over Barreto-Naehrig curves, in CHES 2009, LCNS 5747 (Springer, Berlin, 2009), pp. 254–271

    Google Scholar 

  101. D. Nibouche, A. Bouridane, M. Nibouche, Architectures for Montgomery’s multiplication, in Proceedings of IEE Computers and Digital Techniques, vol. 150, pp. 361–368 (2003)

    Google Scholar 

  102. A. Barenghi, G. Bertoni, L. Breveglieri, G. Pelosi, A FPGA coprocessor for the cryptographic Tate pairing over Fp, in Proceedings of Fifth International Conference on Information Technology: New Generations, ITNG 2008, pp. 112–119 (April 2008)

    Google Scholar 

  103. M. Scott, P.S.L.M. Barreto, Compressed pairings, in CRYPTO, Lecture Notes in Computer Science, vol. 3152, pp. 140–156 (2004)

    Google Scholar 

Further Reading

  • E. Savas, M. Nasser, A.A.A. Gutub, C.K. Koc, Efficient unified Montgomery inversion with multi-bit shifting, in Proceedings of IEE Computers and Digital Techniques, vol. 152, pp. 489–498 (2005)

    Google Scholar 

  • A.F. Tenca, G. Todorov, C.K. Koc, High radix design of a scalable modular multiplier, in Proceedings of Third International Workshop on Cryptographic Hardware and Embedded Systems, CHES, pp. 185–201 (2001)

    Google Scholar 

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    P. V. Ananda Mohan

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Ananda Mohan, P.V. (2016). RNS in Cryptography. In: Residue Number Systems. Birkhäuser, Cham. https://doi.org/10.1007/978-3-319-41385-3_10

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