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Conclusions and Future Work

  • Taimur Rabuske
  • Jorge Fernandes
Chapter
  • 1.2k Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

This chapter discusses the contributions of this book, compares the measurements results with the state-of-the-art, and offers suggestions for future work.

Keywords

L1 VLP Good Matching Characteristics High Energetic Efficiency Similar Aspect Ratio Voltage Booster 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    J. Craninckx, G. van der Plas, A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, New York, 2007), pp. 246–600. doi:10.1109/ISSCC.2007.373386
  2. 2.
    V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, J. Craninckx, An 82μw 9b 40MS/s noise-tolerant dynamic-SAR ADC in 90nm digital CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, New York, 2008), pp. 238–610. doi:10.1109/ISSCC.2008.4523145 Google Scholar
  3. 3.
    J.-H. Tsai, Y.-J. Chen, M.-H. Shen, P.-C. Huang, 1-V, 8b, 40MS/s, 113μW charge-recycling SAR ADC with a 14μW asynchronous controller, in IEEE Symposium on VLSI Circuits (2011), pp. 264–265Google Scholar
  4. 4.
    J.-H. Tsai, Y.-J. Chen, M.-H. Shen, P.-C. Huang, A 70 dB DR 10b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range. IEEE J. Solid State Circuits 49 (5), 1173–1183 (2014). doi:10.1109/JSSC.2014.2309086 CrossRefGoogle Scholar
  5. 5.
    S.-K. Lee, S.-J. Park, H.-J. Park, J.-Y. Sim, A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface. IEEE J. Solid State Circuits 46 (3), 651–659 (2011). ISSN: 0018-9200. doi:10.1109/JSSC2010.2102590
  6. 6.
    H.-Y. Tai, H.-W. Chen, H.-S. Chen, A 3.2fJ/c.-s. 0.35V 10b 100kS/s SAR ADC in 90nm CMOS, in IEEE Symposium on VLSI Circuits (2012), pp. 92–93. ISBN: 978-1-4673-0849-6. doi:1.1109/VLSIC.2012.6243805
  7. 7.
    A. Shikata, R. Sekimoto, T. Kuroda, H. Ishikuro, A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS. IEEE J. Solid State Circuits 47 (4), 1022–1030 (2012). ISSN: 0018-9200. doi:10.1109/JSSC.2012.2185352
  8. 8.
    C.-Y. Liou, C.-C. Hsieh, A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2013), pp. 280–281. doi:10.1109/ISSCC.2013.6487735
  9. 9.
    P. Harpe, E. Cantatore, A. van Roermund, A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction, in IEEE International Solid-State Circuits Conference (ISSCC) (2013), pp. 270–271. doi:10.1109/ISSCC.2013.6487730
  10. 10.
    H.-Y. Tai, Y.-S. Hu, H.-W. Chen, H.-S. Chen, A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2014), pp. 196–197. doi:10.1109/ISSCC.2014.6757397
  11. 11.
    W. Liu, P. Huang, Y. Chiu, A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration. IEEE J. Solid State Circuits 46 (11), 2661–2672 (2011). doi:10.1109/JSSC.2011.2163556 CrossRefGoogle Scholar
  12. 12.
    W. Liu, P. Huang, Y. Chiu, A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration, in Proceedings of IEEE Custom Integrated Circuits Conference (CICC) (2012). doi:10.1109/CICC.2012.6330694

Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Taimur Rabuske
    • 1
  • Jorge Fernandes
    • 1
  1. 1.INESC-ID Instituto Superior TécnicoUniversidade de LisboaLisboaPortugal

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