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An 8-Bit 0.35-V CS-ADC with Comparator Offset Auto-Zero and Voltage Boosting

  • Taimur Rabuske
  • Jorge Fernandes
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

This chapter reports the design of a CS-ADC that uses background calibration to mitigate the comparator offset and improve the overall linearity of the ADC. Operation at low voltages is permitted by the use of voltage-boosted switches in the TH and the DAC. We validate these techniques with the design of a low-voltage low-power SAR ADC that operates from a minimum supply voltage of 0.35 V, and up to 0.6 V, suitable for circuits supplied by power harvesters. Fabricated in a 0.13 μm CMOS process, the prototype employs only regular-Vt transistors. It performs at 3 MSps when supplied by 0.6 V and at 200 kSps when supplied by 0.35 V. At 0.35 V, the measured ENOB is 6.4, leading to a FOM of 5.04 fJ/conversion-step.

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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Taimur Rabuske
    • 1
  • Jorge Fernandes
    • 1
  1. 1.INESC-ID Instituto Superior TécnicoUniversidade de LisboaLisboaPortugal

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