Abstract
Comparators are essential components of ADCs and largely affect their overall performance. Among the performance metrics of the comparator, noise is the most difficult to estimate and simulate, especially for circuits that present a time-varying behavior such as clocked comparators. In this chapter, we present a framework for sizing and optimization of comparators which uses periodic steady-state (PSS) and periodic noise (PNOISE) analyses, commonly used for RF circuits, together with an optimization kernel based on evolutionary algorithms. We present a case-study comparator design, which takes into account noise, power, and delay. The results reveal that the proposed framework minimizes these performance metrics and achieves systematic convergence to consistent Pareto fronts in a short timespan of approximately 27 min. Additionally, the accuracy of the PSS/PNOISE noise estimation method is compared to time-consuming transient noise simulations, presenting a difference standard deviation of only 3.47 % between the two methods.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
J. Craninckx, G. van der Plas, A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (IEEE, New York, 2007), pp. 246–600. doi:10.1109/ISSCC.2007.373386
P. Harpe, E. Cantatore, A. van Roermund, A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction, in IEEE International Solid-State Circuits Conference (ISSCC) (2013), pp. 270–271. doi:10.1109/ISSCC.2013.6487730
P. Nuzzo, F. De Bernardinis, P. Terreni, G. Van der Plas, Noise analysis of regenerative comparators for reconfigurable ADC architectures. IEEE Trans. Circuits Syst. Regul. Pap. 55 (6), 1441–1454 (2008). issn: 1549-8328. doi:10.1109/TCSI2008917991
J. Kim, B. Leibowitz, J. Ren, C. Madden, Simulation and analysis of random decision errors in clocked comparators. IEEE Trans. Circuits Syst. Regul. Pap. 56 (8), 1844–1857 (2009). ISSN: 1549-8328. doi:10.1109/TCSI.2009.2028449
K. Kundert, Introduction to RF simulation and its application. IEEE J. Solid State Circuits 34 (9), 1298–1319 (1999). ISSN: 0018-9200. doi:10.1109/4.782091
A. Hajimiri, T. Lee, A general theory of phase noise in electrical oscillators. IEEE J. Solid State Circuits 33 (2), 179–194 (1998). ISSN: 0018-9200. doi:10.1109/4.658619
J. Kim, B. Leibowitz, M. Jeeradit, Impulse sensitivity function analysis of periodic circuits, in IEEE/ACM International Conference on Computer Aided Design (ICCAD) (2008), pp. 386–391. doi:10.1109/ICCAD.2008.4681602
K. Deb, A. Pratap, S. Agarwal, T. Meyarivan, A fast and elitist multi-objective genetic algorithm: NSGA-II. IEEE Trans. Evol. Comput. 6 (2), 182–197 (2002). ISSN: 1089-778X. doi:10.1109/4235.996017
A. Scholten, L. Tiemeijer, R. van Langevelde, R. Havens, A. Zegers-van Duijnhoven, V. Venezia, Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices 50 (3), 618–632 (2003). ISSN: 0018-9383. doi:10.1109/TED.2003.810480
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Rabuske, T., Fernandes, J. (2017). Noise-Aware Synthesis and Optimization of Voltage Comparators. In: Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications . Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-39624-8_5
Download citation
DOI: https://doi.org/10.1007/978-3-319-39624-8_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-39623-1
Online ISBN: 978-3-319-39624-8
eBook Packages: EngineeringEngineering (R0)