Advertisement

Review of SAR ADC Switching Schemes

  • Taimur Rabuske
  • Jorge Fernandes
Chapter
  • 1.3k Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In this chapter, switching schemes commonly employed in SAR ADCs are revisited and compared. A summary indicates that the CS scheme shows compelling features for LVLP applications. Finally, the state of the art in CS-ADCs is reviewed.

Keywords

Switching Scheme Capacitive Array Comparator Input Bottom Array Monotonic Switching 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    J. McCreary, P. Gray, All-MOS charge redistribution analog-to-digital conversion techniques. I. IEEE J. Solid-State Circuits 10 (6), 371–379 (1975). doi: 10.1109/JSSC.1975.1050629
  2. 2.
    C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE J. Solid-State Circuits 45 (4), 731–740 (2010). doi:10.1109/JSSC.2010. 2042254CrossRefGoogle Scholar
  3. 3.
    X. Song, Y. Xiao, Z. Zhu, VCM-based monotonic capacitor switching scheme for SAR ADC. Electron. Lett. 49 (5), 327–329, February 2013. doi: 10.1049/el.2012.3332
  4. 4.
    V. Hariprasath, J. Guerber S.-H. Lee, U.-K. Moon, Merged capacitor switching based SAR ADC with highest switching energy-efficiency. Electron. Lett. 46 (9), 620 (2010). doi: 10.1049/el.2010.0706
  5. 5.
    Y. Zhu, C.-H. Chan, U.-F. Chio, S.-W. Sin, U. Seng-Pan, R.P. Martins, F. Maloberti, A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS. IEEE J. Solid-State Circuits 45 (6), 1111–1121 (2010). doi: 10.1109/JSSC.2010.2048498
  6. 6.
    E. Rahimi, M. Yavari, Energy-efficient high-accuracy switching method for SAR ADCs. Electron. Lett. 50 (7), 499–501 (2014). doi: 10.1049/el.2013.3451 CrossRefGoogle Scholar
  7. 7.
    C. Yuan, Y. Lam, Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electron. Lett. 48 (9), 482 (2012). doi: 10.1049/el.2011.4001
  8. 8.
    J. Craninckx, G. van der Plas, A 65 fJ/conversion-step 0-to-50 MS/s 0- to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) IEEE, February 2007, pp. 246–600. doi:  10.1109/ISSCC.2007.373386
  9. 9.
    B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq, J. Craninckx, A 70 dB DR 10b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range”, in IEEE Int. Solid-State Circuits Conf (ISSCC) IEEE, February 2012, pp. 470–472. doi:1.1109/ISSCC.2012.6177095Google Scholar
  10. 10.
    V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, J. Craninckx, An 82 μw 9b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) IEEE, February 2008, pp. 238–610. doi: 10.1109/ISSCC.2008.4523145
  11. 11.
    J.-H. Tsai, Y.-J. Chen, M.-H. Shen, P.-C. Huang, 1-V, 8b, 40 MS/s, 113 μW charge-recycling SAR ADC with a 14 μW asynchronous controller, in IEEE Symposium VLSI Circuits 2011, pp. 264–265Google Scholar
  12. 12.
    B. Malki, T. Yamamoto, B. Verbruggen, P. Wambacq, J. Craninckx, A 70 dB DR 10b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range. IEEE J. Solid-State Circuits 49 (5), 1173–1183 (2014). doi: 10.1109/JSSC.2014.2309086

Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Taimur Rabuske
    • 1
  • Jorge Fernandes
    • 1
  1. 1.INESC-ID Instituto Superior TécnicoUniversidade de LisboaLisboaPortugal

Personalised recommendations