Experimental Results

  • Ricardo Martins
  • Nuno Lourenço
  • Nuno Horta
Chapter

Abstract

This Chapter presents and discusses the application of the proposed, and implemented, methodologies to practical analog integrated circuit (IC) layout design examples. The framework of the proposed methodology for the automatic generation of analog ICs layout is coded in JAVA™, and integrated in the AIDA’s framework (Martins et al., International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012, pp. 29–32; Lourenço et al., Design, Automation & Test in Europe Conference (DATE), 2015, pp. 1156–1161; Martins et al., International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2015, pp. 1–4). Several well-known analog circuit structures for a 130nm design process are studied, including a single stage amplifier using voltage combiner, a single ended two-stage amplifier, a two-stage folded cascode amplifier and an operational transconductance amplifier; and also, placement and routing benchmark sets are used to evaluate each of the developed modules.

Keywords

Analog IC design Automatic layout generation Electronic design automation Fully-automatic Layout-aware sizing Placement Routing User-assisted 

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Copyright information

© Springer International Publishing Switzerland 2017

Authors and Affiliations

  • Ricardo Martins
    • 1
  • Nuno Lourenço
    • 1
  • Nuno Horta
    • 1
  1. 1.Instituto Superior Técnico, Universidade de LisboaInstituto de TelecomunicaçõesLisboaPortugal

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