This chapter covers the template-based placement approach proposed in the tool AIDA-L. In short, this Placer first extracts the topological relations described in a XML template file to a non-slicing B*-tree layout representation (Chang et al., Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC), 2000, pp. 458–463). Then, the B*-tree is packed using the modules, which are instantiated from the AIDA’s analog module generator (AIDA-AMG) (Canelas et al., Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, IGI Global, Hershey, PA, 2014), to generate the floorplan that respects the high level floorplan guidelines provided by the designer. The first section of this chapter covers the overall architecture of the template-based Placer, followed, by the description of the high level floorplan guidelines contained in the template file in section “XML Description for Template-based Placement”. The B*-tree layout representation and extraction procedure are properly detailed in sections “B*-Tree Extraction” and “Instantiation: AIDA’s Analog Module Generator”, and also, a brief overview of the instantiation of the modules and the characteristics of the parametric module generator are provided. In section “B*-Tree Packing”, the floorplan packing from the B*-tree layout representation is overviewed, followed, by a simple illustrative case study.
KeywordsAnalog IC design Automatic placement generation B*-tree floorplan representation Electronic design automation Template descriptions User-assisted
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