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Static Verification of Railway Schema and Interlocking Design Data

Part of the Lecture Notes in Computer Science book series (LNPSE,volume 9707)


The paper presents an experience of verifying a large scale, real-life dataset describing various aspects of railway station design. We discuss how a number of assorted digital artefacts were pooled together and converted into a set-theoretic model over which a type inference procedure is run. The typed model is then used to confirm or contradict logical conjectures over data elements. We employ a number of state-of-the-art SMT solvers as a verification back-end. The project is ongoing but has already identified a number of issues in topology definition and signalling data that were missed by other automated tests and not revealed by simulation tools.


  • Theorem Prove
  • Formal Verification
  • Train Movement
  • Model Check Tool
  • Free Block

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  • DOI: 10.1007/978-3-319-33951-1_9
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  1. Iliasov, A., Lopatkin, I., Romanovsky, A.: Practical formal methods in railways - the SafeCap approach. In: George, L., Vardanega, T. (eds.) Ada-Europe 2014. LNCS, vol. 8454, pp. 177–192. Springer, Heidelberg (2014)

    Google Scholar 

  2. Janczura, C.W.: Modelling and Analysis of Railway Network Control Logic using Coloured Petri Nets. PhD thesis, School of Mathematics and Institute for Telecommunications Research, University of South Australia (1998)

    Google Scholar 

  3. Hagalisletto, A.M., Bjørk, J., Chieh Yu, I., Enger, P.: Constructing and refining large-scale railway models represented by Petri Nets. IEEE Trans. Syst. Man Cybern. Part C 37, 444–460 (2007)

    CrossRef  Google Scholar 

  4. Iliasov, A., Romanovsky, A.: SafeCap domain language for reasoning about safety and capacity. In: Pacific-Rim Dependable Computing Conference (PRDC 2012), Niigata, Japan. IEEE CS, November 2012

    Google Scholar 

  5. Winter, K.: Model checking railway interlocking systems. In: Proceeding of the 25th Australian Computer Science Conference (ACSC 2002) (2002)

    Google Scholar 

  6. Winter, K., Robinson, N.: Modelling large railway interlockings and model checking small ones. In: Proceeding of the Australian Cumputer Science Conference (ACSC 2003) (2003)

    Google Scholar 

  7. Burdy, L.: Automatic refinement. In: Proceedings of BUGM at FM 1999 (1999)

    Google Scholar 

  8. Lecomte, T., Burdy, L., Leuschel, M.: Formally checking large data sets in the railways. CoRR, abs/1210.6815 (2012)

    Google Scholar 

  9. Leuschel, M., Butler, M.: ProB: a model checker for B. In: Araki, K., Gnesi, S., Mandrioli, D. (eds.) FME 2003. LNCS, vol. 2805, pp. 855–874. Springer, Heidelberg (2003)

    CrossRef  Google Scholar 

  10. OpenTrack simulator.

  11. Abo, R., Voisin, L.: Formal implementation of data validation for railway safety-related systems with OVADO. In: Counsell, S., Núñez, M. (eds.) SEFM 2013. LNCS, vol. 8368, pp. 221–236. Springer, Heidelberg (2014)

    CrossRef  Google Scholar 

  12. RailSys simulation platform.

  13. TPTP. Thousands of Problems for Theorem Provers.

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Correspondence to Alexei Iliasov .

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Iliasov, A., Stankaitis, P., Adjepon-Yamoah, D. (2016). Static Verification of Railway Schema and Interlocking Design Data. In: Lecomte, T., Pinger, R., Romanovsky, A. (eds) Reliability, Safety, and Security of Railway Systems. Modelling, Analysis, Verification, and Certification. RSSRail 2016. Lecture Notes in Computer Science(), vol 9707. Springer, Cham.

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  • Print ISBN: 978-3-319-33950-4

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