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Static Verification of Railway Schema and Interlocking Design Data

  • Alexei IliasovEmail author
  • Paulius Stankaitis
  • David Adjepon-Yamoah
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9707)

Abstract

The paper presents an experience of verifying a large scale, real-life dataset describing various aspects of railway station design. We discuss how a number of assorted digital artefacts were pooled together and converted into a set-theoretic model over which a type inference procedure is run. The typed model is then used to confirm or contradict logical conjectures over data elements. We employ a number of state-of-the-art SMT solvers as a verification back-end. The project is ongoing but has already identified a number of issues in topology definition and signalling data that were missed by other automated tests and not revealed by simulation tools.

Keywords

Theorem Prove Formal Verification Train Movement Model Check Tool Free Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Alexei Iliasov
    • 1
    Email author
  • Paulius Stankaitis
    • 1
  • David Adjepon-Yamoah
    • 1
  1. 1.Newcastle UniversityNewcastle upon TyneUK

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