Hardware Accelerator to Compute the Minimum Embedding Dimension of ECG Records
In this paper, a parallel hardware implementation to accelerate the computation of the minimum embedding dimension is presented. The estimation of the minimum embedding dimension is a time-consuming task necessary to start the non-linear analysis of biomedical signals. The design presented has as main goals maximum performance and reconfigurability. The design process is explained, giving details on the decisions taken to achieve massive parallelization, as well as the methodology used to reduce hardware usage while keeping a high mathematical accuracy. The results yield that hardware acceleration achieves a speedup of three orders of magnitude in comparison to a purely software approach.
KeywordsClock Cycle Reference Vector Takens Vector Hardware Accelerator FPGA Device
We thank Altera University Program for the support given to the Laboratory of Bioengineering, University CEU-San Pablo. This research was partially supported by the University CEU-San Pablo under project PPC12/2014.
- 3.Kantz, H., Schreiber, T.: Human ECG: nonlinear deterministic versus stochastic aspects. In: IEE Proceedings- Science, Measurement and Technology, vol. 145, pp. 279–284. IET (1998)Google Scholar
- 10.Pereda, E., Gonzalez, J., Bhattacharya, J., Rial, R.: Nonlinear Analysis of Biomedical Data. University of La Laguna Press, Tenerife (2010)Google Scholar