Hardware Accelerator to Compute the Minimum Embedding Dimension of ECG Records

  • Pablo Pérez-Tirador
  • Gabriel Caffarena
  • Constantino A. García
  • Abraham Otero
  • Rafael Raya
  • Rodrigo Garcia-Carmona
Conference paper

DOI: 10.1007/978-3-319-31744-1_23

Part of the Lecture Notes in Computer Science book series (LNCS, volume 9656)
Cite this paper as:
Pérez-Tirador P., Caffarena G., García C.A., Otero A., Raya R., Garcia-Carmona R. (2016) Hardware Accelerator to Compute the Minimum Embedding Dimension of ECG Records. In: Ortuño F., Rojas I. (eds) Bioinformatics and Biomedical Engineering. IWBBIO 2016. Lecture Notes in Computer Science, vol 9656. Springer, Cham

Abstract

In this paper, a parallel hardware implementation to accelerate the computation of the minimum embedding dimension is presented. The estimation of the minimum embedding dimension is a time-consuming task necessary to start the non-linear analysis of biomedical signals. The design presented has as main goals maximum performance and reconfigurability. The design process is explained, giving details on the decisions taken to achieve massive parallelization, as well as the methodology used to reduce hardware usage while keeping a high mathematical accuracy. The results yield that hardware acceleration achieves a speedup of three orders of magnitude in comparison to a purely software approach.

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Pablo Pérez-Tirador
    • 1
  • Gabriel Caffarena
    • 2
  • Constantino A. García
    • 3
  • Abraham Otero
    • 2
  • Rafael Raya
    • 2
  • Rodrigo Garcia-Carmona
    • 2
  1. 1.Department of Medical Physics and Biomedical EngineeringUniversity College LondonLondonUK
  2. 2.University CEU-San PabloMadridSpain
  3. 3.Centro Singular de Investigación en Tecnoloxías da Información (CiTIUS)University of Santiago de CompostelaSantiago de CompostelaSpain

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