Abstract
A fundamental research question given the dark silicon problem is how best to leverage the abundance of transistors on the chip. In this chapter, we describe two solutions to this problem. In the first, we exploit the inherent variations in process parameters that exist in scaled technologies to offer increased performance. Since process variations result in core-to-core variations in power and frequency, the idea is to cherry pick the best subset of cores for an application so as to maximize performance within the power budget. Second, we describe an approach for synthesis of micro-architecturally dark silicon chip multi-processors. The goal is to determine the optimal number of cores of each type to provision the processor with, such that the area and power budgets are met and the application performance is maximized.
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Garg, S., Turakhia, Y., Marculescu, D. (2017). Heterogeneous Dark Silicon Chip Multi-Processors: Design and Run-Time Management. In: Rahmani, A., Liljeberg, P., Hemani, A., Jantsch, A., Tenhunen, H. (eds) The Dark Side of Silicon. Springer, Cham. https://doi.org/10.1007/978-3-319-31596-6_4
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DOI: https://doi.org/10.1007/978-3-319-31596-6_4
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