Brain–Machine Interface: System Optimization

  • Amir ZjajoEmail author


To develop neural prostheses capable of interfacing with neuron cells and neural networks, multichannel probes and the electrodes need to be customized to the anatomy and morphology of the recording site. The increasing density and the miniaturization of the functional blocks in these multielectrode arrays, however, presents significant circuit design challenge in terms of area, power, and the scalability, reliability and expandability of the recording system. In this chapter, we propose a novel method for power per area (PPA) optimization under yield constrains in multichannel neural recording interface. Using a sequence of minimizations with iteratively generated low-dimensional subspaces, our approach renders consistently improved PPA ratio and imposes no restrictions on the distribution of process parameters or how the data enters the constraints. The proposed method can be used with any variability model and subsequently any correlation model, and is not restricted by any particular performance constraint. The experimental results, obtained on the multichannel neural recording interface circuits implemented in CMOS 90 nm technology, demonstrate power savings of up to 26 % and area of up to 22 % without yield penalty.


Flicker Noise Lyapunov Equation Noise Power Spectral Density Nonlinear Circuit Stochastic Differential Equation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Delft University of TechnologyDelftThe Netherlands

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