Advertisement

Switched-Capacitor DC–DC in Bulk CMOS for On-Chip Power Granularization

  • Hans Meyvaert
  • Michiel Steyaert
Chapter
  • 642 Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

Recent trends show that the power management unit (PMU) to supply System-on-Chip solutions is undergoing a transformation and is taking a leap toward monolithic integration [31, 39, 130]. This is a necessary evolution because of multiple market requirements. On the one hand, modern electronic systems are forced to be more energy efficient. This can follow from constraints on heat dissipation, where lower losses result in a lower overall dissipated heat, or to increase the battery autonomy in mobile systems. On the other hand, monolithic integration enables to reduce the form factor of power converters, saving on the required PCB board space. On top of that, the solution thickness can be reduced [122], which has become an important differentiation in modern high-end smartphones. In order to improve system efficiency and form factor reduction, these systems frequently rely on energy saving techniques, such as Adaptive Voltage Scaling (AVS), Dynamic Voltage Scaling (DVS), Dynamic Frequency Scaling (DFS), power and clock gating to realize (deep, etc.) sleep, multiple supply voltages with voltage islands and power domains, and so on. Consequently, the step toward integrated power conversion is a key enabler for the aforementioned techniques because it allows power delivery to take place via a distributed or granular concept, yielding the possibility of many voltage domains. In fact, once power converters are integrated on chip, the concept of having one centralized power converter becomes obsolete. There is no longer a reason to keep the power converter in one place besides tradition, which is not a rational motivation and leads to bad circuit design [30].

Keywords

Switching Frequency Output Impedance Dynamic Voltage Scaling Voltage Ripple Parasitic Capacitor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 9.
    S. Ben-Yaakov, On the influence of switch resistances on switched-capacitor converter losses. IEEE Trans. Ind. Electron. 59(1), 638–640 (2012)CrossRefGoogle Scholar
  2. 10.
    H. Bergveld, K. Nowak, R. Karadi, S. Iochem, J. Ferreira, S. Ledain, E. Pieraerts, M. Pommier, A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration, in IEEE Energy Conversion Congress and Exposition, 2009 (ECCE 2009) (2009), pp. 3698–3705Google Scholar
  3. 13.
    L. Chang, R.K. Montoye, B.L. Ji, A.J. Weger, K.G. Stawiasz, R.H. Dennard, A fully-integrated switched-capacitor 2:1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm2, in Proceedings of Symposium on VLSI Circuits (2010), pp. 55–56Google Scholar
  4. 17.
    J.F. Dickson, On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique. IEEE J. Solid State Circuits 11(3), 374–378 (1976)CrossRefGoogle Scholar
  5. 23.
    R. Ghaida, G. Torres, P. Gupta, Single-mask double-patterning lithography for reduced cost and improved overlay control. IEEE Trans. Semicond. Manuf. 24(1), 93–103 (2011)CrossRefGoogle Scholar
  6. 27.
    R. Guo, Z. Liang, A.Q. Huang, A family of multimodes charge pump based DC-DC converter with high efficiency over wide input and output range. IEEE Trans. Power Electron. 27(11), 4788–4798 (2012)CrossRefGoogle Scholar
  7. 28.
    J.M. Henry, J.W. Kimball, Switched-capacitor converter state model generator. IEEE Trans. Power Electron. 27(5), 2415–2425 (2012)CrossRefGoogle Scholar
  8. 30.
    V.V. Ivanov, I.M. Filanovsky, Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology (Kluwer, Dordrecht, 2004)Google Scholar
  9. 31.
    R. Jain, B. Geuskens, S. Kim, M. Khellah, J. Kulkarni, J. Tschanz, V. De, A 0.45–1 V fully-integrated distributed switched capacitor DC-DC converter with high density MIM capacitor in 22 nm tri-gate CMOS. IEEE J. Solid State Circuits 49(4), 917–927 (2014)Google Scholar
  10. 38.
    S. Kose, E.G. Friedman, Effective resistance of a two layer mesh. IEEE Trans. Circuits Syst. Express Briefs 58(11), 739–743 (2011)CrossRefGoogle Scholar
  11. 39.
    V. Kursun, S. Narendra, V. De, E. Friedman, Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. Very Large Scale Integr. VLSI Syst. 11(3), 514–522 (2003)CrossRefGoogle Scholar
  12. 41.
    H.-P. Le, M. Seeman, S.R. Sanders, V. Sathe, S. Naffziger, E. Alon, A 32 nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency, in Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2010), pp. 210–211Google Scholar
  13. 42.
    H.-P. Le, S.R. Sanders, E. Alon, Design techniques for fully integrated switched-capacitor DC-DC converters. IEEE J. Solid State Circuits 46(9), 2120–2131 (2011)CrossRefGoogle Scholar
  14. 43.
    H.-P. Le, J. Crossley, S. Sanders, E. Alon, A sub-ns response fully integrated battery-connected switched-capacitor voltage regulator delivering 0.19 W/mm2 at 73% efficiency, in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2013), pp. 372–373Google Scholar
  15. 53.
    M.S. Makowski, D. Maksimovic, Performance limits of switched-capacitor DC-DC vonverters, in Proceedings of IEEE Power Electronics Specialists Conference (PESC), vol. 2 (1995), pp. 1215–1221Google Scholar
  16. 56.
    H. Meyvaert, T. Van Breussegem, M. Steyaert, A monolithic 0.77 W/mm2 power dense capacitive DC-DC step-down converter in 90 nm Bulk CMOS, in 2011 Proceedings of the European Solid-State Circuits Conference (ESSCIRC) (2011), pp. 483–486Google Scholar
  17. 63.
    A.V. Mezhiba, E.G. Friedman, Impedance characteristics of power distribution grids in nanoscale integrated circuits. IEEE Trans. Very Large Scale Integr. VLSI Syst. 12(11), 1148–1155 (2004)CrossRefGoogle Scholar
  18. 70.
    V.W. Ng, M.D. Seeman, S.R. Sanders, Minimum PCB footprint point-of-load DC-DC converter realized with switched-capacitor architecture, in Proceedings of IEEE Energy Conversion Congress and Exposition (ECCE) (2009), pp. 1575–1581Google Scholar
  19. 71.
    L. Ni, D.J. Patterson, J.L. Hudgins, High power current sensorless bidirectional 16-phase interleaved DC-DC converter for hybrid vehicle application. IEEE Trans. Power Electron. 27(3), 1141–1151 (2012)CrossRefGoogle Scholar
  20. 87.
    A. Sarafianos, M. Steyaert, Fully integrated wide input voltage range capacitive DC-DC converters: the folding Dickson converter. IEEE J. Solid State Circuits 50(7), 1560–1570 (2015)CrossRefGoogle Scholar
  21. 90.
    M.D. Seeman, S.R. Sanders, Analysis and optimization of switched-capacitor DC-DC converters. IEEE Trans. Power Electron. 23(2), 841–851 (2008)CrossRefGoogle Scholar
  22. 95.
    B. Serneels, M. Steyaert, W. Dehaene, A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13μm CMOS, in Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2006), pp. 668–671Google Scholar
  23. 100.
    D. Somasekhar, B. Srinivasan, G. Pandya, F. Hamzaoglu, M. Khellah, T. Karnik, K. Zhang, Multi-phase 1 GHz voltage doubler charge-pump in 32 nm logic process, in 2009 Symposium on VLSI Circuits (2009), pp. 196–197Google Scholar
  24. 101.
    D. Somasekhar, B. Srinivasan, G. Pandya, F. Hamzaoglu, M. Khellah, T. Karnik, K. Zhang, Multi-phase 1 GHz voltage doubler charge pump in 32 nm logic process. IEEE J. Solid State Circuits 45(4), 751–758 (2010)CrossRefGoogle Scholar
  25. 102.
    M. Steyaert, P. Vancorenland, CMOS: a paradigm for low power wireless? in Proceedings of 39th Design Automation Conference (2002), pp. 836–841Google Scholar
  26. 105.
    L. Su, D. Ma, Monolithic reconfigurable SC power converter with adaptive gain control and on-chip capacitor sizing, in Proceedings of IEEE Energy Conversion Congress and Exposition (ECCE) (2010), pp. 2713–2717Google Scholar
  27. 110.
    The international technology roadmap for semiconductors (2009). public.itrs.net.Google Scholar
  28. 113.
    T. Van Breussegem, M. Steyaert, A 82% efficiency 0.5% ripple 16-phase fully integrated capacitive voltage doubler, in 2009 Symposium on VLSI Circuits (2009), pp. 198–199Google Scholar
  29. 115.
    T.M. Van Breussegem, M.S.J. Steyaert, Monolithic capacitive DC-DC converter with single boundary-multiphase control and voltage domain stacking in 90 nm CMOS. IEEE J. Solid State Circuits 46(7), 1715–1727 (2011)CrossRefGoogle Scholar
  30. 116.
    T. Van Breussegem, M. Steyaert, Accuracy improvement of the output impedance model for capacitive down-converters. Analog Integr. Circ. Sig. Process 72(1), 271–277 (2012)CrossRefGoogle Scholar
  31. 119.
    G. Villar Piqué, A 41-phase switched-capacitor power converter with 3.8 mV output ripple and 81% efficiency in baseline 90 nm CMOS, in Proceedings of IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (2012), pp. 98–100Google Scholar
  32. 122.
    G. Villar Piqué, H.J. Bergveld, R. Karadi, A 1W 8-ratio switched-capacitor boost power converter in 140 nm CMOS with 94.5% efficiency, 0.5 mm thickness and 8.1mm2 PCB area, in 2015 Symposium on VLSI Circuits (2015)Google Scholar
  33. 125.
    M. Wens, M. Steyaert, A fully integrated CMOS 800-mW four-phase semiconstant ON/OFF-time step-down converter. IEEE Trans. Power Electron. 26(2), 326–333 (2011)CrossRefGoogle Scholar
  34. 126.
    J. Wibben, R. Harjani, A high-efficiency DC-DC converter using 2 nH integrated inductors. IEEE J. Solid State Circuits 43(4), 844–854 (2008)CrossRefGoogle Scholar
  35. 129.
    B. Zhai, D. Blaauw, D. Sylvester, K. Flautner, The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. Very Large Scale Integr. VLSI Syst. 13(11), 1239–1252 (2005)CrossRefGoogle Scholar
  36. 130.
    B. Zimmer, Y. Lee, A. Puggelli, J. Kwak, R. Jevtic, B. Keller, S. Bailey, M. Blagojevic, P.-F. Chiu, H.-P. Le, P.-H. Chen, N. Sutardja, R. Avizienis, A. Waterman, B. Richards, P. Flatresse, E. Alon, K. Asanovic, B. Nikolic, A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28 nm FDSOI, in 2015 Symposium on VLSI Circuits (2015)Google Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Hans Meyvaert
    • 1
  • Michiel Steyaert
    • 2
  1. 1.Kessel-LoBelgium
  2. 2.LeuvenBelgium

Personalised recommendations