Abstract
As is well known in the industry, the design complexity at 16 nm node and below is exploding. Small form factor requirements and conflicting demands of high performance and low power and small area result in ever so complex design architecture. Multi-core, multi-threading and Power, Performance and Area (PPA) demands exacerbate the design complexity and functional verification thereof.
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© 2016 Springer International Publishing Switzerland
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Mehta, A.B. (2016). Introduction. In: SystemVerilog Assertions and Functional Coverage. Springer, Cham. https://doi.org/10.1007/978-3-319-30539-4_1
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DOI: https://doi.org/10.1007/978-3-319-30539-4_1
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-30538-7
Online ISBN: 978-3-319-30539-4
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