Abstract
In this paper a novel method for data reordering in a video stream is presented. It can be used in high performance vision algorithms that require block based image processing. For case study a block based optical flow histogram computation application was selected. The proposed solution allows for a 2.3x and 6.3x speed-up for fixed-point and floating-point calculations respectively. This enables real-time operations for \(1920 \times 1080\) pixels or higher resolutions.
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Notes
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In some cases, mainly for lower image resolutions, it is possible to use frequency multiplication.
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Otherwise it is not possible to handle a collision.
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Basic hardware resources available in an FPGA: FF – flip-flops, LUT6 - six-input LUT modules, BRAM – block RAM memory of size 18 or 36 kB, SLICE – unit grouping logic resources in Xilinx FPGA, DSP48 – hardware arithmetic unit.
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Acknowledgments
The work presented in this paper was supported by AGH University of Science and Technology project number 15.11.120.476 (first) and 11.11.120.612 (second author).
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Kryjak, T., Gorgon, M., Komorkiewicz, M. (2016). An Efficient Hardware Architecture for Block Based Image Processing Algorithms. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_5
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