Allocation and Schematic Design

  • Paul PopEmail author
  • Wajid Hassan Minhass
  • Jan Madsen


During the physical design of biochips, we have to decide what and how many components to use in the biochip architecture, which is called allocation, and how to interconnect those components using channels, which is called schematic design. The components are allocated from a component library, and are limited by a set of resource constraints, which specify an upper limit on the number of components of each type that should be on the biochip. The output of the allocation and schematic design is a netlist, which is a graph model that captures the components (vertices) and their interconnections (edges). In this chapter we select methods from microelectronics VLSI to be applied for the allocation and schematic design, and modify and extend them for mVLSI biochips. We show the netlists we obtain by applying our algorithms on several benchmarks.


Architectural synthesis Netlist Allocation Schematic design Resource-constrained scheduling 


  1. 1.
    Coussy, P., Morawiec, A.: High-level Synthesis: From Algorithm to Digital Circuit. Springer, New York (2008)CrossRefGoogle Scholar
  2. 2.
    Micheli, G.D.: Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education, New York (1994)Google Scholar
  3. 3.
    Stanford Microfluidic Foundry.
  4. 4.
    Ullman, D.: NP-complete scheduling problems. J. Comput. Syst. Sci. 10, 384–393 (1975)CrossRefMathSciNetzbMATHGoogle Scholar
  5. 5.
    Urbanski, J.P., Thies, W., Rhodes, C., Amarasinghe, S., Thorsen, T.: Digital microfluidics using soft lithography. Lab Chip 6(1), 96–104 (2006)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.Technical University of DenmarkKongens LyngbyDenmark

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