A Scalable Flexible SOM NoC-Based Hardware Architecture

  • Mehdi Abadi
  • Slavisa Jovanovic
  • Khaled Ben Khalifa
  • Serge Weber
  • Mohamed Hédi Bedoui
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 428)


In this paper , a parallel hardware implementation of a self-organizing map (SOM) is presented. Practical scalability and flexibility are the main architecture features which are obtained by using a Network-on-chip (NoC) approach for communication between neurons. The presented hardware architecture allows on-line learning and can be easily adapted for a large variety of applications without a considerable design effort. A hardware \(5\times 5\) SOM was validated through the FPGA implementation and its performances at a working frequency of 200 MHz for a 32-element input vector reach 724 MCUPS in the learning and 1168 MCPS in the recall phase.


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  1. 1.UMR 7198, Institut Jean LamourUniversité de LorraineNancyFrance
  2. 2.LR12ES06, Laboratoire de Technologie Et Imagerie MédicaleUniversité de MonastirMonastirTunisia
  3. 3.Ecole Nationale d’Ingénieurs de SousseUniversité de SousseSousseTunisia

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