Abstract
In Chapters 1 and 2, we studied the device and digital circuit aspects of dual and single work function SNTs with the intention to minimize power dissipation. Both of these studies have determined that silicon nanowire technology is better suited for the future of VLSI in terms of circuit speed and power dissipation compared to dual-gated SOI or FiNFET technologies. These studies also included the weaknesses of SNTs such as increased layout area due to surrounding gate metal thickness, large source resistance caused by source contact extension, and limited ON current caused by fixed transistor geometry. In Chapters 1 and 2, SPICE level 6 models were used in circuit simulations. While these models had acceptable accuracy in producing speed and power dissipation figures for basic CMOS logic gates, more accurate intrinsic device modeling and parasitic RC extraction were required for simulating larger scale digital circuits, analog circuits, and Radio Frequency (RF) circuits. This need prompted us to explore more accurate SPICE models such as BSIMSOI for fully depleted Silicon-On-Insulator (SOI) devices to use in the circuit simulations. This chapter examines how the intrinsic and extrinsic BSIMSOI models were created for NMOS and PMOS SNTs.
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References
Bindal A, Hamedi-Hagh S (2007) An exploratory study on power efficient silicon nanowire dynamic NMOSFET/PMESFET logic. IEE Proc Sci Measurement Technol 1:121–130
Bindal A, Hamedi-Hagh S (2007) Static NMOS circuits using silicon nanowire technology for crossbar architectures. Semicond Sci Tech 22:54–64
Bindal A, Hamedi-Hagh S (2006) The design and analysis of dynamic NMOSFET/PMESFET logic using silicon nanowire technology. Semicond Sci Tech 21:1002–1012
Bindal A, Naresh A, Yuan P, Nguyen KK, Hamedi-Hagh S (2007) The design of dual work function CMOS transistors and circuits using silicon nanowire technology. IEEE Trans Nanotechnol 6:291–302
Bindal A, Hamedi-Hagh S (2006) The impact of silicon nanowire technology on the design of single work function CMOS transistors and circuits. Nanotechnol 17:4340–4351
Bindal A, Hamedi-Hagh S (2007) The design of a new spiking neuron using silicon nanowire technology. Nanotechnol 18:1–12
Bindal A, Hamedi-Hagh S (2007) Silicon nanowire transistors and their applications for the future of VLSI: an exploratory design study of a 16 × 16 SRAM. J Nanoelectron Optoelectron 2:294–303
Pin Su, Fung SKH, Wyatt PW, Wan H, Mansun Chan, Niknejad AM, Hu C (2003) A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. Proceedings of the IEEE custom integrated circuits conference. pp 241–244
Eminente S, Alessandrini M, Fiegna C (2004) Comparative analysis of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs by numerical simulation. Solid State Electron 48:543–549
Kilchytska V, Neve A, Vancaillie L, Levacq D, Adriaensen S, Van Meer H, De Meyer K, Raynaud C, Dehan M, Raskin J, Flandre D (2003) Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Trans Electron Dev 50:577–588
Jimenez D, Iniguez B, Sune J, Saenz J (2004) Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits. J Appl Phys 96:5271–5276
Flandre D, Raskin J, Vanhoenacker D (2001) SOI CMOS transistors for RF microwave applications. Int J High Speed Electron Syst 11:1159–1248
Majima H, Saito Y, Hiramoto T (2001) Impact of quantum mechanical effects on design of nanoscale narrow channel n- and p-type MOSFETs. Technical digest of international electron device meeting. pp 951–954
Woerlee P, Knitel M, Van Langevelde R, Klaassen D, Tiemeijer L, Scholten A, Zegers-Van Duijnhoven A (2001) RF-CMOS performance trends. IEEE Trans Electron Dev 48:1776–1782
Frank D, Dennard R, Nowak E, Solomon PM, Taur Y, Wong HSP (2001) Device scaling limits for Si MOSFETs and their application dependencies. Proc IEEE 89:259–288
Menozzi R, Lanzoni M, Fiegna C, Sangiorgi E, Ricco B (1990) Latch-up testing in CMOS IC’s. IEEE J Solid State Circ 25:1010–1014
Jin W, Eo Y, Shim J, Eisenstadt W, Park M, Yu H (2001) Silicon substrate coupling, noise modeling and experimental verification for mixed signal integrated circuit design. Digest of the IEEE International Microwave Symposium 3:1727–1730
Raskin J, Vivian A, Flandre D, Colinge J (1997) Substrate crosstalk reduction using SOI technology. IEEE Trans Electron Dev 44:2252–2261
Jin X (1998) An effective gate resistance model for CMOS RF and noise modeling. Technical digest of the IEEE electron device meeting. pp 961–964
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Bindal, A., Hamedi-Hagh, S. (2016). SPICE Modeling for Analog and Digital Applications. In: Silicon Nanowire Transistors. Springer, Cham. https://doi.org/10.1007/978-3-319-27177-4_3
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DOI: https://doi.org/10.1007/978-3-319-27177-4_3
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