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Stencil Computations on HPC-oriented ARMv8 64-Bit Multi-Core Processor

  • Chunjiang Li
  • Yushan Dong
  • Kuan Li
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9530)

Abstract

The ARMv8 64-bit platform has been considered as an alternative for high performance computing (HPC). Stencil computations are a class of iterative kernels which update array elements according to a stencil. In this paper, we evaluate the performance and scalability of one ARMv8 64-bit Multi-Core Processor with 7-point 3D stencil code, and a series of optimization are devised for the stencil code. In the optimization, we mainly focus on how to parallelize the kernel and how to exploit data locality with loop tiling, also we improve the calculation of the block size in tiling. The achieved performance differs with the grid size of stencil, and the optimal performance is 24.4 % of the peak DP Flops for the grid size of \(64^{3}\). Comparing with Intel Xeon processor, the performance of the ARMv8 64-bit processor is about 40 % of that of Sandy Bridge for the stencil code with the grid size of \(512^{3}\), but this ARMv8 64-bit processor shows better scalability.

Keywords

Stencil computation ARMv8 64-bit multi-core processor Parallelization Loop tiling 

Notes

Acknowledgements

The work in this paper is partially supported by the project of National Science Foundation of China under grant No.61170046, and the National High Technology Research and Development Program of China (863 Program) No.2012AA0 10903.

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Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.School of ComputerNational University of Defence TechnologyChangshaChina

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