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Parallelizing Block Cryptography Algorithms on Speculative Multicores

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Algorithms and Architectures for Parallel Processing (ICA3PP 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9528))

Abstract

Although block cryptography algorithms have been parallelized into different platforms, they have not yet been explored on speculative multicore architecture thoroughly, especially under CBC, CFB and OFB modes. This paper presents a study of parallelizing several block cryptography algorithms (AES, 3DES, RC5 and TWOFISH) on a novel speculative multicore architecture, including its speculative execution mechanism, architectural design and programming model. It illustrates both application and kernel level speculative speedups in these applications under all ECB, CBC, CFB and OFB modes. The experimental results show that: (1) in ECB mode, all the block cryptography algorithms perform well on speculative multicore platform. It can achieve similar speedup compared with graphics processors (GPU) while provides a more friendly programmability. (2) In CBC and CFB modes, decryption kernel in these applications still can get a promising 15.6x–25.6x speedup. (3) 32 cores’ computing resources can be used efficiently in the model.

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References

  1. Munir, A., Ranka, S., Gordon-Ross, A.: High-performance energy-efficient multicore embedded computing. IEEE Trans. Parallel Distrib. Syst. 23(4), 684–700 (2012)

    Article  Google Scholar 

  2. Tian, C., Lin, C., Feng, M., Gupta, R.: Enhanced speculative parallelization via incremental recovery. In: Proceedings of the 16th ACM Symposium on Principles and Practice of Parallel Programming, San Antonio, TX, USA (2011)

    Google Scholar 

  3. Feng, M., Gupta, R., Hu, Y.: SpiceC: scalable parallelism via implicit copying and explicit commit. In: Proceedings of the 16th ACM Symposium on Principles and Practice of Parallel Programming, San Antonio, TX, USA, pp. 69–80 (2011)

    Google Scholar 

  4. Udupa, A., Rajan, K., Thies, W.: ALTER: exploiting breakable dependences for parallelization. ACM SIGPLAN Not. 46(6), 480–491 (2011)

    Article  Google Scholar 

  5. Prabhu, M.K., Olukotun, K.: Exposing speculative thread parallelism in SPEC2000. In: 10th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Chicago, IL, USA (2005)

    Google Scholar 

  6. Kejariwal, A., Tian, X., et al.: On the performance potential of different types of speculative thread-level parallelism. In: 20th Annual International Conference on Supercomputing, Cairns, Queensland, Australia (2006)

    Google Scholar 

  7. Xekalakis, P., Ioannou, N., Cintra, M.: Combining thread level speculation helper threads and runahead execution. In: 23rd International Conference on Supercomputing, pp. 410–420 (2009)

    Google Scholar 

  8. Harrison, O., Waldron, J.: AES encryption implementation and analysis on commodity graphics processing units. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 209–226. Springer, Heidelberg (2007)

    Chapter  Google Scholar 

  9. Elbirt, A.J., Yip, W., Chetwynd, B., Paar, C.: An FPGAbased performance evaluation of the AES block cipher candidate algorithm finalists. IEEE Trans. Very Large Scale Integr. Syst. 9(4), 545–557 (2001)

    Article  Google Scholar 

  10. Chen, T., Raghavan, R., Dale, J.N., Iwata, E.: Cell broadband engine architecture and its first implementation - a performance view. IBM J. Res. Dev. 51(5), 559–572 (2007)

    Article  Google Scholar 

  11. Cook, D.L., Ioannidis, J., Keromytis, A.D., Luck, J.: CryptoGraphics: secret key cryptography using graphics cards. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol. 3376, pp. 334–350. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  12. Sohi, G.S., Breach, S.E., Vijaykumar, T.N.: Multiscalar processors. In: 22nd Annual International Symposium on Computer Architecture (ISCA 1995), Barcelona, Spain (1995)

    Google Scholar 

  13. Hammond, L., Hubbert, B.A., Siu, M., Parbhu, M.K., Chen, M., Qlukotun, K.: The Stanford hydra CMP. IEEE Micro 20(2), 71–84 (2000)

    Article  Google Scholar 

  14. Chen, M.K., and Olukotun, K.: The Jrpm system for dynamically parallelizing Java programs. In: International Symposium on Computer Architecture, pp. 434–445 (2003)

    Google Scholar 

  15. Rul, S., Vandierendonck, H., De Bosschere, K.: Function level parallelism driven by data dependencies. ACM SIGARCH Comput. Archit. News 35(1), 55–62 (2007)

    Article  Google Scholar 

  16. Oplinger, J.T., Heine, D.L., Lam, M.S.: In search of speculative thread-level parallelism. In: PACT 1999, pp. 303–313 (1999)

    Google Scholar 

  17. Binkert, N., Beckmann, B., Black, G., et al.: The gem5 simulator. ACM SIGARCH Comput. Archit. News 39(2), 1–7 (2011)

    Article  Google Scholar 

  18. Johnson, T.A., Eigenmann, R., Vijaykumar, T.N.: Speculative thread decomposition through empirical optimization. In: 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 205–214 (2007)

    Google Scholar 

  19. Tian, C., Feng, M., Gupta, R.: Speculative parallelization using state separation and multiple value prediction. ACM SIGPLAN Not. 45(8), 63–72 (2010)

    Google Scholar 

  20. Raman, A., Kim, H., Mason, T.R., et al.: Speculative parallelization using software multi-threaded transactions. ACM SIGARCH Comput. Archit. News 38(1), 65–76 (2010)

    Article  Google Scholar 

  21. Liu, Y., An, H., Li, X., Leng, P., Sun, S., Chen, J.: VSCP: a cache controlling method for improving single thread performance in multicore system. In: 14th IEEE International Conference on High Performance Computing and Communications, pp. 161–168 (2012)

    Google Scholar 

  22. Li, G., An, H., Li, Q., Deng, B., Dai, W.: Efficient execution of speculative threads and transactions with hardware transactional memory. Future Gener. Comput. Syst. 30, 242–253 (2014)

    Article  Google Scholar 

  23. Ren, Y., An, H., Sun, T., Cong, M., Wang, Y.: Dynamic resource tuning for flexible core chip multiprocessors. In: Hsu, C.-H., Yang, L.T., Park, J.H., Yeo, S.-S. (eds.) ICA3PP 2010, Part I. LNCS, vol. 6082, pp. 32–41. Springer, Heidelberg (2010)

    Chapter  Google Scholar 

  24. Sun, T., An, H., et al.: CRQ-based fair scheduling on composable multicore architectures. In: 26th ACM SIGARCH International Conference on Supercomputing (ICS 2012), pp. 173–184 (2012)

    Google Scholar 

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Acknowledgement

This work is supported financially by the National Natural Science Foundation of China grants 61202044, the National Basic Research Program of China under contract 2011CB302501, the National Hi-tech Research and Development Program of China under contracts 2012AA010902, the Research Fund of Southwest University of Science and Technology 12zxwk08.

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Authors and Affiliations

  1. Department of Computer Science and Technology, Southwest University of Science and Technology, Mianyang, 621010, China

    Yaobin Wang, Zhiqin Liu, Lei Zhang & Qingfeng Wang

  2. Department of Computer Science and Technology, University of Science and Technology of China, Hefei, 230027, China

    Yaobin Wang, Hong An, Lei Zhang & Qingfeng Wang

Authors
  1. Yaobin Wang
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  2. Hong An
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  3. Zhiqin Liu
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  4. Lei Zhang
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  5. Qingfeng Wang
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Corresponding author

Correspondence to Yaobin Wang .

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Editors and Affiliations

  1. Central South University, Changsha, China

    Guojun Wang

  2. The University of Sydney, Sydney, New South Wales, Australia

    Albert Zomaya

  3. University of Murcia, Murcia, Murcia, Spain

    Gregorio Martinez

  4. Hunan University , Changsha, China

    Kenli Li

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Wang, Y., An, H., Liu, Z., Zhang, L., Wang, Q. (2015). Parallelizing Block Cryptography Algorithms on Speculative Multicores. In: Wang, G., Zomaya, A., Martinez, G., Li, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2015. Lecture Notes in Computer Science(), vol 9528. Springer, Cham. https://doi.org/10.1007/978-3-319-27119-4_1

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  • DOI: https://doi.org/10.1007/978-3-319-27119-4_1

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-27118-7

  • Online ISBN: 978-3-319-27119-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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