Spin-Based CMOS-Compatible Devices

  • Viktor SverdlovEmail author
  • Siegfried Selberherr
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9374)


With CMOS feature size rapidly approaching scaling limits the electron spin attracts attention as an alternative degree of freedom for low-power non-volatile devices. Silicon is perfectly suited for spin-driven applications, because it is mostly composed of nuclei without spin and is characterized by weak spin-orbit interaction. Elliot-Yafet spin relaxation due to phonons’ mediated scattering is the main mechanism in bulk silicon at room temperature. Uniaxial stress dramatically reduces the spin relaxation, particularly in thin silicon films. Lifting the valley degeneracy completely in a controllable way by means of standard stress techniques represents a major breakthrough for spin-based devices. Despite impressive progress regarding spin injection, the larger than predicted signal amplitude is still heavily debated. In addition, the absence of a viable concept of spin manipulation in the channel by electrical means makes a practical realization of a device working similar to a MOSFET difficult. An experimental demonstration of such a spin field-effect transistor (SpinFET) is pending for 25 years now, which at present is a strong motivation for researchers to look into the subject. Commercially available CMOS compatible spin-transfer torque magnetic random access memory (MRAM) built on magnetic tunnel junctions possesses all properties characteristic to universal memory: fast operation, high density, and non-volatility. The critical current for magnetization switching and the thermal stability are the main issues to be addressed. A substantial reduction of the critical current density and a considerable increase of the thermal stability are achieved in structures with a recording layer between two vertically sandwiched layers, where the recording layer is composed of two parts in the same plane next to each other. MRAM can be used to build logic-in-memory architectures with non-volatile storage elements on top of CMOS logic circuits. Non-volatility and reduced interconnect losses guarantee low-power consumption. A novel concept for non-volatile logic-in-memory circuits utilizing the same MRAM cells to store and process information simultaneously is proposed.


Spin Relaxation Magnetic Tunnel Junction Bloch Sphere Recording Layer Magnetic Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



This work is supported by the European Research Council through the grant #247056 MOSILSPIN.


  1. 1.
    Appelbaum, I., Huang, B., Monsma, D.J.: Electronic measurement and control of spin transport in Silicon. Nature 447, 295–298 (2007)CrossRefGoogle Scholar
  2. 2.
    Huang, B., Monsma, D.J., Appelbaum, I.: Coherent spin transport through a 350 micron thick silicon wafer. Phys. Rev. Lett. 99, 177209 (2007)CrossRefGoogle Scholar
  3. 3.
    Jansen, R.: Silicon spintronics. Nat. Mater. 11, 400–408 (2012)CrossRefGoogle Scholar
  4. 4.
    Datta, S., Das, B.: Electronic analog of the electro-optic modulator. Appl. Phys. Lett. 56, 665–667 (1990)CrossRefGoogle Scholar
  5. 5.
    Sugahara, S., Nitta, J.: Spin-transistor electronics: an overview and outlook. Proc. IEEE 98, 2124–2154 (2010)CrossRefGoogle Scholar
  6. 6.
    Schmidt, G., Ferrand, D., Molenkamp, L.W., Filip, A.T., van Wees, B.J.: Fundamental obstacle for electrical spin injection from a ferromagnetic metal into a diffusive semiconductor. Phys. Rev. B 62, R4790–R4793 (2000)CrossRefGoogle Scholar
  7. 7.
    Rashba, E.I.: Theory of electrical spin injection: tunnel contacts as a solution of the conductivity mismatch problem. Phys. Rev. B 62, R16267–R16270 (2000)CrossRefGoogle Scholar
  8. 8.
    Dash, S.P., Sharma, S., Patel, R.S., de Jong, M.P., Jansen, R.: Electrical creation of spin polarization in silicon at room temperature. Nature 462, 491–494 (2009)CrossRefGoogle Scholar
  9. 9.
    Li, C., van’t Erve, O., Jonker, B.: Electrical injection and detection of spin accumulation in silicon at 500K with magnetic metal/silicon dioxide contacts. Nat. Commun. 2, 245 (2011)CrossRefGoogle Scholar
  10. 10.
    Jansen, R., Deac, A.M., Saito, H., Yuasa, S.: Injection and detection of spin in a semiconductor by tunneling via interface states. Phys. Rev. B 85, 134420 (2012)CrossRefGoogle Scholar
  11. 11.
    Song, Y., Dery, H.: Magnetic-field-modulated resonant tunneling in ferromagnetic-insulator-nonmagnetic junctions. Phys. Rev. Lett. 113, 047205 (2014)CrossRefGoogle Scholar
  12. 12.
    Zutic, I., Fabian, J., Das Sarma, S.: Spintronics: fundamentals and applications. Rev. Mod. Phys. 76, 323–410 (2004)CrossRefGoogle Scholar
  13. 13.
    Fabian, J., Matos-Abiaguea, A., Ertler, C., Stano, P., Zutic, I.: Semiconductor spintronics. Acta Phys. Slovaca 57, 565–907 (2007)CrossRefGoogle Scholar
  14. 14.
    Cheng, J.L., Wu, M.W., Fabian, J.: Theory of the spin relaxation of conduction electrons in silicon. Phys. Rev. Lett. 104, 016601 (2010)CrossRefGoogle Scholar
  15. 15.
    Li, P., Dery, H.: Spin-orbit symmetries of conduction electrons in silicon. Phys. Rev. Lett. 107, 107203 (2011)CrossRefGoogle Scholar
  16. 16.
    Song, Y., Dery, H.: Analysis of phonon-induced spin relaxation processes in silicon. Phys. Rev. B 86, 085201 (2012)CrossRefGoogle Scholar
  17. 17.
    Li, J., Appelbaum, I.: Modeling spin transport in electrostatically-gated lateral-channel silicon devices: role of interfacial spin relaxation. Phys. Rev. B 84, 165318 (2011)CrossRefGoogle Scholar
  18. 18.
    Li, J., Appelbaum, I.: Lateral spin transport through bulk silicon. Appl. Phys. Lett. 100, 162408 (2012)CrossRefGoogle Scholar
  19. 19.
    Osintsev, D., Baumgartner, O., Stanojevic, Z., Sverdlov, V., Selberherr, S.: Subband splitting and surface roughness induced spin relaxation in (001) silicon SOI MOSFETs. Solid-State Electron. 90, 34–38 (2013)CrossRefGoogle Scholar
  20. 20.
    Sverdlov, V.: Strain-Induced Effects in Advanced MOSFETs. Springer, Wien - New York (2011)CrossRefGoogle Scholar
  21. 21.
    Jancu, J.M., Girard, J.C., Nestoklon, M.O., Lemaître, A., Glas, F., Wang, Z.Z., Voisin, P.: STM images of subsurface Mn Atoms in GaAs: evidence of hybridization of surface and impurity states. Phys. Rev. Lett. 101, 196801 (2008)CrossRefGoogle Scholar
  22. 22.
    Prada, M., Klimeck, G., Joynt, R.: Spin-orbit splittings in Si/SiGe quantum wells: from ideal Si membranes to realistic heterostructures. New J. Phys. 13, 013009 (2011)CrossRefGoogle Scholar
  23. 23.
    Wilamowski, Z., Jantsch, W.: Suppression of spin relaxation of conduction electrons by cyclotron motion. Phys. Rev. B 69, 035328 (2004)CrossRefGoogle Scholar
  24. 24.
    Osintsev, D., Sverdlov, V., Stanojevi\(\grave{\rm c}\), Z., Makarov, A., Selberherr, S.: Temperature dependence of the transport properties of spin field-effect transistors built with InAs and Si channels. Solid-State Electron. 71, 25–29 (2012)Google Scholar
  25. 25.
    Slonczewski, J.: Current-driven excitation of magnetic multilayers. J. Magn. Magn. Mater. 159, L1–L7 (1996)CrossRefGoogle Scholar
  26. 26.
    Berger, L.: Emission of spin waves by a magnetic multilayer traversed by a current. Phys. Rev. B 54, 9353–9358 (1996)CrossRefGoogle Scholar
  27. 27.
    Makarov, A., Sverdlov, V., Osintsev, D., Selberherr, S.: Reduction of switching time in pentalayer magnetic tunnel junctions with a composite-free layer. Phys. Status Solidi - Rapid Res. Lett. 5, 420–422 (2011)CrossRefGoogle Scholar
  28. 28.
    Makarov, A., Sverdlov, V., Selberherr, S.: Magnetic tunnel junctions with a composite free layer: a new concept for future universal memory. In: Luryi, S., Xu, J., Zaslavsky, A. (eds.) Future Trends in Microelectronics, pp. 93–101. Wiley, New York (2013)CrossRefGoogle Scholar
  29. 29.
    Makarov, A.: Modeling of emerging resistive switching based memory cells. Dissertation, Institute for Microelectronics, TU Wien (2014)Google Scholar
  30. 30.
    Endoh, T.: STT-MRAM technology and its NV-logic applications for ultimate power management. In: 2014 CMOS Emerging Technologies Research (CMOSETR), p. 14 (2014)Google Scholar
  31. 31.
    Natsui, M., Suzuki, D., Sakimura, N., Nebashi, R., Tsuji, Y., Morioka, A., Sugibayashi, T., Miura, S., Honjo, H., Kinoshita, K., Ikeda, S., Endoh, T., Ohno, H., Hanyu, T.: Nonvolatile logic-in-memory array processor in 90 nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. In: 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 194–195 (2013)Google Scholar
  32. 32.
    Lyle, A., Harms, J., Patil, S., Yao, X., Lilja, D.J., Wang, J.P.: Direct communication between magnetic tunnel junctions for nonvolatile logic fan-out architecture. Appl. Phys. Lett. 97, 152504 (2010)CrossRefGoogle Scholar
  33. 33.
    Lyle, A., Patil, S., Harms, J., Glass, B., Yao, X., Lilja, D., Wang, J.: Magnetic tunnel junction logic architecture for realization of simultaneous computation and communication. IEEE Trans. Magn. 47, 2970–2973 (2011)CrossRefGoogle Scholar
  34. 34.
    Mahmoudi, H., Windbacher, T., Sverdlov, V., Selberherr, S.: Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory. Solid-State Electron. 84, 191–197 (2013)CrossRefGoogle Scholar
  35. 35.
    Borghetti, J., Snider, G., Kuekes, P., Yang, J., Stewart, D., Williams, R.: Memristive switches enable stateful logic operations via material implication. Nature 464, 873–876 (2010)CrossRefGoogle Scholar
  36. 36.
    Mahmoudi, H., Windbacher, T., Sverdlov, V., Selberherr, S.: Reliability analysis and comparison of implication and reprogrammable logic gates in magnetic tunnel junction logic circuits. IEEE Trans. Magn. 49, 5620–5628 (2013)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.Institute for MicroelectronicsTU WienViennaAustria

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