Abstract
This chapter provides background information for readers who are interested in the philosophy and technology behind FPGAs. We present this from a software engineer’s viewpoint without hiding the hardware specific characteristics of FPGAs. The chapter discusses the architecture and programming models as well as the pros and cons of CPUs, GPUs and FPGAs. The operation of FPGAs will be described as well as the major steps that are needed to map a circuit description on an FPGA. This will provide a deep enough understanding of the characteristics of an FPGA and how this helps in accelerating certain parts of an application.
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Notes
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- 2.
The limit is probably less what is available, but what is affordable. The high capacity flagship devices of the two major FPGA vendors Xilinx and Altera typically cost over 10 k US$. So the limit is often not a technological, but an economical one. However when Xilinx for example introduced its new Series-7 FPGAs, the smallest Kintex-7 device (XC7K70T) provided at a price tag below 100 US$ significantly more resources than its Virtex-2 flagship (XC2V8000) a decade ago. So in other words, what is far too expensive today might be well affordable very soon.
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Most available FPGAs in these days can be partially reconfigured. This allows some parts of the FPGA to be operational (e.g., a CPU controlling and managing the system and a memory controller) while changing some accelerator modules. Partial reconfiguration can be used for a time-multiplexing of FPGA resources (e.g., if a problem does not fit the device). This helps for better utilizing an FPGA (and hence allowing for using a smaller and therefore cheaper and less power hungry device). This technique can also be used to speed-up computations. Then, instead of providing a chain of smaller modules concurrently on the FPGA, we might use reconfiguration to load only the module currently needed, such that we have more resources available for each module. This can then be used for exploiting a higher level of parallelization, which in turn can eventually speedup processing significantly. Finally, partial reconfiguration can be used for implementing dynamically instantiating hardware modules in a system (e.g., for creating a hardware thread at runtime). More comprehensive information on partial runtime reconfiguration is provided in [Koc13].
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In an article from EETimes it is stated that “Microsemi already has over 1000 FPGAs in every Airbus A380” (http://www.electronics-eetimes.com/?cmp_id=7&news_id=222914228).
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Despite that FPGAs are basically made from multiplexers, it is a bit ironic that they are not very good at implementing multiplexers using their reconfigurable logic cells. In the case we want to implement multiplexers with many inputs, this would cost a considerable number of logic cells.
References
C. Bobda. Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications. Springer, 2007.
V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
J. Cong and Y. Ding. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 13(1):1–12, Jan 1994.
R. H. Dennard, F. H. Gaensslen, H. nien Yu, V. L. Rideout, E. Bassous, Andre, and R. Leblanc. Design of ion-implanted MOSFETs with very small physical dimensions. IEEE J. Solid-State Circuits, 87(4):668–678, 1974.
R. J. Francis, J. Rose, and K. Chung. Chortle: A technology mapping program for lookup table-based field programmable gate arrays. In Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC ’90, pages 613–619, New York, NY, USA, 1990. ACM.
D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin. High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, Norwell, MA, USA, 1992.
N. Goulding-Hotta, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, V. Bhatt, J. Babb, S. Swanson, and M. Taylor. The GreenDroid mobile application processor: An architecture for silicon’s dark future. IEEE Micro, 31(2):86–95, March–April 2011.
S. Hauck and A. DeHon. Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2007.
D. Koch, C. Beckhoff, and J. Teich. ReCoBus-Builder: A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAs. In Field Programmable Logic and Applications, FPL 2008. International Conference on, pages 119 –124, sept. 2008.
D. Koch. Partial Reconfiguration on FPGAs – Architectures, Tools and Applications. Springer, 2013.
I. Kuon and J. Rose. Measuring the gap between FPGAs and ASICs. In Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, (FPGA) ’06, pages 21–30, New York, NY, USA, 2006. ACM.
L. Mcmurchie and C. Ebeling. Pathfinder: A negotiation-based performance-driven router for FPGAs. In Proceedings of the 1995 ACM third International Symposium on Field-Programmable Gate Arrays (FPGA), pages 111–117, 1995.
G. Moore. Cramming more components onto integrated circuits. Electronics, 38(8):114–117, April 1965.
A. Putnam, A. M. Caulfield, E. S. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. P. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Y. Xiao, and D. Burger. A reconfigurable fabric for accelerating large-scale datacenter service. In Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pages 13–24. IEEE, 2014.
A. Rodchenko, A. Nisbet, A. Pop, and M. Lujan. Effective barrier synchronization on Intel Xeon Phi coprocessor. In 20th International Conference on Parallel Processing (Euro-Par), (Springer 2015), pp. 588–600.
J. Robinson, S. Vafaee, J. Scobbie, M. Ritche, and J. Rose. The supersmall soft processor, in VI Southern Programmable Logic Conference (SPL) (2010), pp 3–8.
E. Vermij, L. Fiorin, C. Hagleitner, and K. Bertels. Exascale radio astronomy: Can we ride the technology wave? In J. Kunkel, T. Ludwig, and H. Meuer, editors, Supercomputing, volume 8488 of Lecture Notes in Computer Science, pages 35–52. Springer International Publishing, 2014.
M. Yue, D. Koch, and G. Lemieux. Rapid overlay builder for xilinx FPGAs. In Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on, pages 17–20, May 2015.
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Koch, D., Ziener, D., Hannig, F. (2016). FPGA Versus Software Programming: Why, When, and How?. In: Koch, D., Hannig, F., Ziener, D. (eds) FPGAs for Software Programmers. Springer, Cham. https://doi.org/10.1007/978-3-319-26408-0_1
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