Modeling Logic Gates and Circuits with Generalized Nets

  • Lenko Erbakanov
  • Todor Kostadinov
  • Todor Petkov
  • Sotir Sotirov
  • Veselina Bureva
Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 401)

Abstract

In this paper, modeling of logic gates is presented for the first time. Four models of Generalized Nets (GN)—AND gate, a binary to decimal decoder, delay type flip-flop, n-bit binary counter and logical circuits are presented in the following paper. Here we also suggest using the recently proposed approach of InterCriteria Analysis, based on index matrices and intuitionistic fuzzy sets, which aim to detect possible correlations between pairs of criteria. We can perform the measurements, if we have a set of several logical circuits that can be used to obtain identical output data. The aforementioned logical circuits must be composed of different logical elements. By using several measurement points and different schematics, we can suggest the best solution for the considered type of task.

Keywords

Generalized nets Digital logic Intercriteria analysis 

Notes

Acknowledgements

The authors are grateful for the support provided by the National Science Fund of Bulgaria under grant DFNI-I-02-5/2014 and the Project NIH-355, 2015 of University “Prof. Asen Zlatarov”.

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Lenko Erbakanov
    • 1
  • Todor Kostadinov
    • 1
  • Todor Petkov
    • 1
  • Sotir Sotirov
    • 1
  • Veselina Bureva
    • 1
  1. 1.Intelligent Systems LaboratoryUniversity Professor Dr. Assen ZlatarovBurgasBulgaria

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