Results and Discussion

  • Semeen Rehman
  • Muhammad Shafique
  • Jörg Henkel


This chapter presents reliability improvement results of the proposed cross-layer reliability optimization flow (integrating all the novel contributions of this manuscript) compared to state-of-the-art single-layer reliability optimizing techniques. Evaluation of individual contributions compared to their relevant state-of-the-art techniques has already been presented in the respective chapters, i.e., Chaps.  4 and  5. First the processor synthesis, aging estimation, and process variation maps are presented in Sect. 7.1. Section 7.2 presents different benchmark applications from the MiBench benchmark suite [111]. Section 7.3 presents an overview of comparison partners, parameters considered for evaluation, and an overview of the results explained in subsequent sections. Section 7.4 presents the summary of comparison results for various chip sizes, numerous process variation maps, and various scenarios of simultaneously executing applications. Sections 7.5 and 7.6 present more in-depth results for different chip sizes, different application scenarios, and selected chips, respectively.


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Semeen Rehman
    • 1
  • Muhammad Shafique
    • 2
  • Jörg Henkel
    • 2
  1. 1.CES – Chair for Embedded SystemsKarlsruhe Institute of TechnologyKarlsruheGermany
  2. 2.Department of Computer ScienceKarlsruhe Institute of TechnologyKarlsruheGermany

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