Software Program-Level Reliability Optimization for Dependable Code Generation
State-of-the-art has primarily exploited the compiler-level techniques for improving the performance and energy. This chapter aims at enabling reliability-driven compilation enabled by the instruction-level reliability models of Chap. 4 that quantify the reliability-wise importance of different instructions and the impact of their interdependencies on the vulnerability variations. This chapter presents several novel techniques for reliable code generation in order to increase software program’s reliability under user-provided tolerable performance overhead constraints. Improved software reliability can be achieved in two orthogonal and equally important ways: (1) Reducing the error probabilities by reducing the vulnerabilities to soft errors and critical instruction executions; and (2) Error detection and recovery through instruction duplication or triplication, where selective redundancy can be applied to reduce the performance overhead.
KeywordsCritical Instruction Reliability Improvement Performance Overhead Loop Unroll Instruction Execution
- 27.N. Oh, P. Shirvani, and E. McCluskey, “Error detection by duplicated instructions in super-scalar processors”, in IEEE Transactions on Reliability, vol. 51, no. 1, pp. 63–75, 2002.Google Scholar
- 28.G. Reis, J. Chang, N. Vachharajani, R. Rangan, D. August, and S. Mukherjee, “Software-controlled fault tolerance”, in ACM Transactions on Architecture and Code Optimization (TACO), vol. 2, no. 4, pp. 366–396, 2005.Google Scholar
- 34.N. Oh, P. Shirvani, and E. McCluskey, “Control-flow checking by software signatures”, in IEEE Transactions on Reliability, vol. 51, no. 1, pp. 111–122, 2002.Google Scholar
- 71.G. Reis, “Software modulated fault tolerance”, Ph.D. Thesis, Princeton University, 2008.Google Scholar
- 76.D. Borodin and B. Juurlink, “Protective redundancy overhead reduction using instruction vulnerability factor”, in Proceedings of the 7th ACM International Conference on Computing Frontiers, pp. 319–326, 2010.Google Scholar
- 77.J. Hu, S. Wang, and G. Ziavras, “In-register duplication: Exploiting narrow-width value for improving register file reliability”, in IEEE International Conference on Dependable Systems and Networks (DSN 2006), pp. 281–290, 2006.Google Scholar
- 78.P. Lokuciejewski and P. Marwedel, “Combining worst-case timing models, loop unrolling, and static loop analysis for WCET minimization”, in 21st IEEE Euromicro Conference on Real-Time Systems (ECRTS), pp. 35–44, 2009.Google Scholar
- 80.J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. Irwin, “Compiler-directed instruction duplication for soft error detection”, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp. 1056–1057, 2005.Google Scholar
- 81.J. Xu, Q. Tan, and R. Shen, “The Instruction Scheduling for Soft Errors based on Data Flow Analysis”, in IEEE Pacific Rim International Symposium on Dependable Computing, pp. 372–378, 2009.Google Scholar
- 92.R. Venkatasubramanian, J. Hayes, and B. Murray, “Low cost online fault detection using control flow assertions”, in Proceedings of 9th IEEE On-Line Test. Symposium (IOLTS), pp. 137–143, 2003.Google Scholar
- 129.GCC: https://gcc.gnu.org/.
- 133.J. Yan and W. Zhang, “Compiler guided register reliability improvement against soft errors”, in IEEE International Conference on Embedded Software (EMSOFT), pp. 203–209, 2005.Google Scholar
- 134.J. Cong and K. Gururaj, “Assuring Application-Level Correctness Against Soft Errors”, in IEEE International Conference on Computer Aided Design (ICCAD), pp. 150–157, 2011.Google Scholar