Abstract
This chapter deals with design of Mealy FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Mealy FSMs are discussed. In this case, only one EMB is enough for implementing the circuit. Next, the optimization methods are discussed based on encoding of the collections of microoperations and replacement of logical conditions. Also, the methods are discussed based on encoding of the rows of FSM structure table. All these methods lead to two-level models of Mealy FSMs. Next, these methods are combined together for further optimizing the hardware amount in FSM logic circuits. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. The Chapter includes a lot of tables with results of investigations of proposed methods for the standard benchmarks.
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Barkalov, A., Titarenko, L., Kolopienczyk, M., Mielcarek, K., Bazydlo, G. (2016). Design of EMB-Based Mealy FSMs. In: Logic Synthesis for FPGA-Based Finite State Machines. Studies in Systems, Decision and Control, vol 38. Springer, Cham. https://doi.org/10.1007/978-3-319-24202-6_7
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DOI: https://doi.org/10.1007/978-3-319-24202-6_7
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