Advertisement

Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems

  • Manel Ammar
  • Mouna Baklouti
  • Maxime Pelcat
  • Karol Desnos
  • Mohamed Abid
Conference paper
Part of the Studies in Computational Intelligence book series (SCI, volume 612)

Abstract

Massively Parallel Multi-Processors System-on-Chip (MP2SoC) architectures require efficient programming models and tools to deal with the massive parallelism present within the architecture. In this paper, we propose a tool which automates the generation of the System-Level Architecture Model (S-LAM) from a Unified Modeling Language-based (UML) model annotated with the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) profile. The S-LAM-based description of the MP2SoC architecture is conformed to the IP-XACT standard. The integration of our generator within a co-design framework provides the specification of the whole MP2SoC system using UML and MARTE. Then, gradual refinements allow the execution of a rapid prototyping process.

Keywords

Design Space Exploration Model Drive Engineer Component Instance Hierarchic Class Transformation Engine 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Engelmann, C., Lauer, F.: Facilitating co-design for extreme-scale systems through lightweight simulation. In IEEE International Conference on Cluster Computing Workshops and Posters, CLUSTER WORKSHOPS, 2010, pp. 1–8 September 2010Google Scholar
  2. 2.
    Lugato, D., Bruel, J-M., Ober, I.: Model-Driven Engineering for High Performance Computing Applications. In: S. Cakaj (ed.) Modeling Simulation and Optimization-Focus on Applications (2010)Google Scholar
  3. 3.
    Object Management Group. Unified Modeling Language specification, version 2.1. Available: http://www.omg.org/spec/UML/2.1.2/Infrastructure/PDF
  4. 4.
    Ecker, W., Müller, W., Dömer, R.: Hardware-Dependent Software, pp. 1–13. Springer, Netherlands (2009)CrossRefGoogle Scholar
  5. 5.
    IEEE standard for IP-XACT, standard structure for packaging, integrating, and reusing IP within tools flows, IEEE Std 1685-2009, February 2010, pp. C1-360Google Scholar
  6. 6.
    Object Management Group. UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems, version 1.0. Available: http://www.omg.org/spec/MARTE/1.0/PDF/
  7. 7.
    Pelcat, M., Desnos, K., Heulot, J., Guy, C., Nezan, J.-F., Aridhi, S.: Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming. In \(6^{th}\) European Embedded Design in Education and Research Conference. EDERC 2014, pp. 36–40 (2014)Google Scholar
  8. 8.
    Ochoa-Ruiz, G., Labbani, O., Bourennane, E.-B., et al.: A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile. Des. Autom. Embed. Syst. 16(3), 93–128 (2012)CrossRefGoogle Scholar
  9. 9.
    Herrera, F., Posadas, H., Villar, E., Calvo, D.: Enhanced IP-XACT platform descriptions for automatic generation from UML/MARTE of fast performance models for DSE. In \(15^{th}\) Euromicro Conference on Digital System Design, DSD 2012, pp. 692–699, September 2012Google Scholar
  10. 10.
    Herrera, F., Villar, E.: A Framework for the Generation from UML/MARTE Models of IP-XACT HW Platform Descriptions for Multi-Level Performance Estimation. Proceedings of the Forum of Design and Specification Languages, FDL’2011, November 2011Google Scholar
  11. 11.
    Object Management Group. UML profile for System on a Chip, version 1.0. Available: http://www.omg.org/spec/SoCP/1.0/PDF/
  12. 12.
    Graf, S., Ober, I., Ober, I.: A real-time profile for UML. Int. J. Softw. Tools Technol. Trans. 8(2), 113–127 (2006)CrossRefGoogle Scholar
  13. 13.
    El Mrabti, A., Pétrot, F., Bouchhima, A.: Extending IP-XACT to support an MDE based approach for SoC design. In Design, Automation and Test in Europe Conference and Exhibition, DATE’09, pp. 586–589, April 2009Google Scholar
  14. 14.
  15. 15.
    Ammar, M., Baklouti, M., Pelcat, M., Desnos, K., Abid, M.: MARTE to \(\pi \)SDF transformation for data-intensive applications analysis. In Conference on Design and Architectures for Signal and Image Processing, DASIP, October 2014Google Scholar
  16. 16.
    Pelcat, M., Menuet, P., Aridhi, S., Nezan, J.F.: Scalable compile-time scheduler for multi-core architectures. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE’09, pp. 1552–1555, April 2009Google Scholar
  17. 17.
    Guduric, P., Puder, A., Todtenhofer, R.: A comparison between relational and operational QVT mappings. In the \(6^{th}\) International Conference on Information Technology: New Generations, ITNG ’09, pp.266–271, April 2009Google Scholar
  18. 18.

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Manel Ammar
    • 1
  • Mouna Baklouti
    • 1
  • Maxime Pelcat
    • 2
  • Karol Desnos
    • 2
  • Mohamed Abid
    • 1
  1. 1.CES LaboratoryNational Engineering School of SfaxSfaxTunisia
  2. 2.IETR, INSA RennesCNRS UMR 6164, UEBRennesFrance

Personalised recommendations