Modeling Universal Instruction Selection

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 9255)


Instruction selection implements a program under compilation by selecting processor instructions and has tremendous impact on the performance of the code generated by a compiler. This paper introduces a graph-based universal representation that unifies data and control flow for both programs and processor instructions. The representation is the essential prerequisite for a constraint model for instruction selection introduced in this paper. The model is demonstrated to be expressive in that it supports many processor features that are out of reach of state-of-the-art approaches, such as advanced branching instructions, multiple register banks, and SIMD instructions. The resulting model can be solved for small to medium size input programs and sophisticated processor instructions and is competitive with LLVM in code quality. Model and representation are significant due to their expressiveness and their potential to be combined with models for other code generation tasks.


Constraint Programming Pattern Graph Constraint Model Program Graph Register Allocation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.SCALE, School of ICTKTH Royal Institute of TechnologyStockholmSweden
  2. 2.SCALESwedish Institute of Computer ScienceKistaSweden

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