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Improving Memory Access Performance of In-Memory Key-Value Store Using Data Prefetching Techniques

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Book cover Advanced Parallel Processing Technologies (APPT 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9231))

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Abstract

In-memory Key-Value stores (IMKVs) provide significantly higher performance than traditional disk-based counterparts. As memory technologies advance, IMKVs become practical for modern Big Data processing, which include financial services, e-commerce, telecommunication network, etc. Recently, various IMKVs have been proposed from both academia and industrial. In order to leverage high performance random access capability of main memory, most IMKVs employ hashing based index structures to retrieve data according to keys. Consequently, a regular memory access pattern can be observed in data retrieval from those IMKVs. Normally speaking, one access to index (hash table), which is also located in main memory, is followed by another memory access to value data. Such a regular access pattern provides a potential opportunity that data prefetching techniques can be employed to improve memory access efficiency for data retrieval in these IMKVs. Based on this observation, we explore various data prefetching techniques with proper architecture level modifications on memory controller considering trade-off between design overhead and performance. Specifically, we focus on two key design issues of prefetching techniques: (1) where to fetch data (i.e. data address)? and (2) how many data to fetch (i.e. data size)? Experimental results demonstrate that memory access performance can be substantially improved up to 35.4 %. In addition, we also demonstrate the overhead of prefetching on power consumption.

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References

  1. Intel 64 and IA-32 Architectures Software Developers Manuals. www.intel.com/products/processor/manuals

  2. Memcached. http://memcached.org/

  3. Redis. http://redis.io/

  4. Cattell, R.: Scalable SQLA and NoSQL data stores. SIGMOD Rec. 39(4), 12–27 (2011)

    Article  Google Scholar 

  5. Chang, F., Dean, J., Ghemawat, S., Hsieh, W.C., Wallach, D.A., Burrows, M., Chandra, T., Fikes, A., Gruber, R.E.: Bigtable: a distributed storage system for structured data. ACM Trans. Comput. Syst. 26(2), 4:1–4:26 (2008)

    Article  Google Scholar 

  6. Cooper, B.F., Silberstein, A., Tam, E., Ramakrishnan, R., Sears, R.: Benchmarking cloud serving systems with YCSB. In: Proceedings of the 1st ACM Symposium on Cloud Computing, pp. 143–154. ACM (2010)

    Google Scholar 

  7. DeCandia, G., Hastorun, D., Jampani, M., Kakulapati, G., Lakshman, A., Pilchin, A., Sivasubramanian, S., Vosshall, P., Vogels, W.: Dynamo: Amazon’s highly available key-value store. In: Proceedings of the 21st ACM Symposium on Operating Systems Principles, SOSP 2007, pp. 205–220. ACM, New York (2007)

    Google Scholar 

  8. Fan, B., Andersen, D.G., Kaminsky, M.: MemC3: compact and concurrent memcache with dumber caching and smarter hashing. In: Proceedings of the 10th USENIX Conference on Networked Systems Design and Implementation, NSDI 2013, pp. 371–384. USENIX Association, Berkeley (2013)

    Google Scholar 

  9. Jiménez, V., Cazorla, F.J., Gioiosa, R., Buyuktosunoglu, A., Bose, P., O’Connell, F.P., Mealey, B.G.: Adaptive prefetching on POWER7: improving performance and power consumption. ACM Trans. Parallel Comput. 1(1), 4:1–4:25 (2014)

    Article  Google Scholar 

  10. Kocberber, O., Grot, B., Picorel, J., Falsafi, B., Lim, K., Ranganathan, P.: Meet the walkers: accelerating index traversals for in-memory databases. In: Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 46, pp. 468–479. ACM, New York (2013)

    Google Scholar 

  11. Lakshman, A., Malik, P.: Cassandra: a decentralized structured storage system. SIGOPS Oper. Syst. Rev. 44(2), 35–40 (2010)

    Article  Google Scholar 

  12. Lee, C.J., Mutlu, O., Narasiman, V., Patt, Y.N.: Prefetch-aware DRAM controllers. In: Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 41, pp. 200–209. IEEE Computer Society, Washington, DC (2008)

    Google Scholar 

  13. Lee, C.J., Narasiman, V., Mutlu, O., Patt, Y.N.: Improving memory bank-level parallelism in the presence of prefetching. In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42, pp. 327–336. ACM, New York (2009)

    Google Scholar 

  14. Liao, S.w., Hung, T.H., Nguyen, D., Chou, C., Tu, C., Zhou, H.: Machine learning-based prefetch optimization for data center applications. In: Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, SC 2009, pp. 56:1–56:10. ACM, New York (2009)

    Google Scholar 

  15. Lim, H., Han, D., Andersen, D.G., Kaminsky, M.: MICA: a holistic approach to fast in-memory key-value storage. In: 11th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2014, pp. 429–444. USENIX Association, Seattle (2014)

    Google Scholar 

  16. Loos, P.D.P., Lechtenbrger, J., Vossen, G., Zeier, A., Krger, J., Mller, J., Lehner, W., Kossmann, D., Fabian, B., Gnther, O., Winter, R.: In-memory databases in business information systems. Bus. Inf. Syst. Eng. 3(6), 389–395 (2011)

    Article  Google Scholar 

  17. Luk, C.K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V.J., Hazelwood, K.: Pin: building customized program analysis tools with dynamic instrumentation. In: ACM Sigplan Notices, vol. 40, pp. 190–200. ACM (2005)

    Google Scholar 

  18. Nishtala, R., Fugal, H., Grimm, S., Kwiatkowski, M., Lee, H., Li, H.C., McElroy, R., Paleczny, M., Peek, D., Saab, P., Stafford, D., Tung, T., Venkataramani, V.: Scaling memcache at Facebook. In: Presented as part of the 10th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2013, pp. 385–398. USENIX, Lombard (2013)

    Google Scholar 

  19. Ortega, D., Ayguadé, E., Baer, J.L., Valero, M.: Cost-effective compiler directed memory prefetching and bypassing. In: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques, PACT 2002, pp. 189–198. IEEE Computer Society, Washington, DC (2002)

    Google Scholar 

  20. Plattner, H., Zeier, A.: In-memory Data Management: Technology and Applications. Springer Science & Business Media, Heidelberg (2012)

    Book  Google Scholar 

  21. Rosenfeld, P., Cooper-Balis, E., Jacob, B.: DRAMSim2: a cycle accurate memory system simulator. Comput. Archit. Lett. 10(1), 16–19 (2011)

    Article  Google Scholar 

  22. Rumble, S.M., Kejriwal, A., Ousterhout, J.K.: Log-structured memory for DRAM-based storage. In: Schroeder, B., Thereska, E. (eds.) Proceedings of the 12th USENIX Conference on File and Storage Technologies, FAST 2014, Santa Clara, CA, USA, 17–20 February 2014. pp. 1–16. USENIX (2014)

    Google Scholar 

  23. Sinharoy, B., Kalla, R., Starke, W.J., Le, H.Q., Cargnoni, R., Van Norstrand, J.A., Ronchetti, B.J., Stuecheli, J., Leenstra, J., Guthrie, G.L., Nguyen, D.Q., Blaner, B., Marino, C.F., Retter, E., Williams, P.: IBM POWER7 multicore server processor. IBM J. Res. Dev. 55(3), 1:1–1:29 (2011)

    Article  Google Scholar 

  24. Stuecheli, J.: Next Generation POWER microprocessor. http://www.hotchips.org/archives/2010s/hc25/

  25. Wu, C.J., Jaleel, A., Martonosi, M., Steely, Jr., S.C., Emer, J.: PACMan: prefetch-aware cache management for high performance caching. In: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 44, pp. 442–453. ACM, New York (2011)

    Google Scholar 

  26. Wu, Y.: Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching. In: Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation, PLDI 2002, pp. 210–221. ACM, New York (2002)

    Google Scholar 

  27. Yedlapalli, P., Kotra, J., Kultursay, E., Kandemir, M., Das, C.R., Sivasubramaniam, A.: Meeting midway: improving CMP performance with memory-side prefetching. In: Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, PACT 2013, pp. 289–298. IEEE Press, Piscataway (2013)

    Google Scholar 

  28. Zhao, C., Mei, K., Zheng, N.: Design of write merging and read prefetching buffer in DRAM controller for embedded processor. Microprocess. Microsyst. 38(5), 451–457 (2014)

    Article  Google Scholar 

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Acknowledgements

This work was partially supported by National High-tech R&D Program of China (2013AA013201) and in part by National Natural Science Foundation of China (61202072, 61272132, 61221062).

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Correspondence to PengFei Zhu .

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Zhu, P., Sun, G., Wang, P., Chen, M. (2015). Improving Memory Access Performance of In-Memory Key-Value Store Using Data Prefetching Techniques. In: Chen, Y., Ienne, P., Ji, Q. (eds) Advanced Parallel Processing Technologies. APPT 2015. Lecture Notes in Computer Science(), vol 9231. Springer, Cham. https://doi.org/10.1007/978-3-319-23216-4_1

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  • DOI: https://doi.org/10.1007/978-3-319-23216-4_1

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