New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation

  • Khaled Salah Mohamed
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

Now, SystemVerilog (SV)/UVM gradually dominate the verification landscape. SV does not support MACROS and the language alone was insufficient to enable widespread adoption of the best-practice verification techniques that inspired its development that is why we need UVM [1, 2]. UVM is a methodology for SoC functional verification that uses TLM standard for communication between blocks and SystemVerilog for its languages, or in other words, it uses SV for creating components and TLM for interconnects between components.

Keywords

Trends UVM Localization scan-chain methodology GA Test generation SystemVerilog OOP DPI Randomization Constrained Infrastructure Drawbacks Opportunities Metric Watchdog Library 

References

  1. 1.
    Bromley J (2013) If systemverilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language. In: 2013 Forum on Specification & Design Languages (FDL), IEEE, ParisGoogle Scholar
  2. 2.
    Oliveira FS, Haedicke F, Drechsler R, Kuznik C, Le HM, Ecker W, Mueller W, Große D, Esen V (2012) The system verification methodology for advanced TLM verification. In: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, ACM, New York, pp 313–322Google Scholar
  3. 3.
    Zhaohui H, Pierres A, Shiqing H, Fang C, Royannez P, See EP, Hoon YL (2012) Practical and efficient SOC verification flow by reusing IP testcase and testbench. In: 2012 International SoC Design Conference (ISOCC), IEEE, Jeju Island, pp 175–178Google Scholar
  4. 4.
    Raghuvanshi S, Singh V (2014) Review on universal verification methodology (UVM) concepts for functional verification. Int J Electr Electron Data Commun 2(3):101–107Google Scholar
  5. 5.
    Young-Nam Yun (2011) Beyond UVM for practical SoC verification. In: International SoC design conference (ISOCC), IEEE, Jeju, pp 158–162Google Scholar
  6. 6.
    Sutherland S, Mills D (2013) Synthesizing systemverilog: busting the myth that systemverilog is only for verification. SNUG Silicon Valley 2013. http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf
  7. 7.
    Vaidya B, Pithadiya N (2013) An introduction to universal verification methodology. J Inf Knowl Res Electron Commun Eng 2(02):420–424Google Scholar
  8. 8.
    Spear C, Tumbush G (2012) Systemverilog for verification—a guide to learning the testbench language features, 2nd edn. Springer, New YorkGoogle Scholar
  9. 9.
    Sohofi H, Navabi Z (2014) Assertion-based verification for system-level designs. In: Proceedings of 15th International Symposium on Quality Electronic Design (ISQED), IEEE, Santa Clara, pp 582–588Google Scholar
  10. 10.
    Sutherland S, Mills D (2014) Can my synthesis compiler do that? What ASIC and FPGA synthesis compilers support in the systemverilog-2012 standard. In: Presented at DVCon-2014, San JoseGoogle Scholar
  11. 11.
    Oh Y-J, Song G-Y (2014) System-level verification platform using systemverilog layered testbench & systemC OOP. Int J Control Autom Syst 7(2):221–230CrossRefGoogle Scholar
  12. 12.
    Vijayan U, Anjo CA, Vignesh Raja B, Arun Kumar N (2013) Development of basic template environment for functional verification of VLSI design using UVM. Int J Emerg Technol Adv Eng 3(12):214–216Google Scholar
  13. 13.
    Wile B, Goss JC, Roesne W (2005) Comprehensive functional verification the complete industry cycle. Elsevier, San FranciscoGoogle Scholar
  14. 14.
    Accellera (2011) Universal verification methodology (UVM) 1.1 user’s guide. Cedence Design System, San JoseGoogle Scholar
  15. 15.
    Vörtler T, Klotz T, Einwich K, et al. (2014) Enriching UVM in systemC with AMS extensions for randomization ad functional coverage. In: Conference—Design and Verification Conference & Exhibition Europe (DVCon Europe), MunichGoogle Scholar
  16. 16.
  17. 17.
  18. 18.
    Constantinides K, Mutlu O, Austin TM (2008) Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. In: International Symposium on Microarchitecture (MICRO), IEEE, Lake Como, pp 282–293Google Scholar
  19. 19.
    Park SB, Mitra S (2009) IFRA: Post-silicon bug localization in processors. In: Proceedings of IEEE International High Level Design Validation and Test Workshop, 2007. HLVDT 2007, IEEE, Irvine, pp 154–159Google Scholar
  20. 20.
    Chang K, Wagner I, Bertacco V, Markov I (2007) Automatic error diagnosis and correction for RTL designs. In: Proceedings of IEEE International High Level Design Validation and Test Workshop, 2007. HLVDT 2007, IEEE, Irvine, pp 65–72Google Scholar
  21. 21.
    Mirzaeian S, Zheng F, Cheng K (2008) RTL error diagnosis using a word-level SAT-solver. In: International Test Conference (ITC), IEEE, Santa Clara, pp 1–8Google Scholar
  22. 22.
    Brummayer R, Biere A (2009) Boolector: an efficient SMT solver for bit-vectors and arrays. In: Proceedings of 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, York, pp 174–177Google Scholar
  23. 23.
    Safarpour S, Veneris A (2009) Automated design debugging with abstraction and refinement. IEEE Trans Comput Aided Des Integr Circuits Syst 28(10):1597–1608CrossRefGoogle Scholar
  24. 24.
    Peischl B, Wotawa F (2006) Automated source-level error localization in hardware designs. IEEE Des Test Comput 23(1):8–19CrossRefGoogle Scholar
  25. 25.
    Matsumoto T, Ono S, Fujita M (2012) An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. In: 20th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), IEEE, Santa CruzGoogle Scholar
  26. 26.
    Wong WE, Debroy V, Choi B (2010) A family of code coverage-based heuristics for effective fault localization. J Syst Softw 83(2):188–208CrossRefGoogle Scholar
  27. 27.
    Wong WE, Wei T (2008) A crosstab-based statistical method for effective fault localization. In: Proceedings of the First International Conference on Software Testing, Verification and Validation (ICST), Lillehammer, pp 42–51Google Scholar
  28. 28.
    Jones JA, Harrold MJ (2005) Empirical evaluation of the Tarantula automatic fault-localization technique. In: Proceedings of International Conference on Automated Software Engineering, New York, pp 273–283Google Scholar
  29. 29.
    Rau J, Chien C, Ma J (2005) Reconfigurable multiple scan-chains for reducing test application time of SOCs. In: IEEE International Symposium on Circuits and Systems (ISCAS), pp 5846–5849Google Scholar
  30. 30.
    Mavroidis I, Papaefstathiou I (2009) Accelerating emulation and providing full chip observability and controllability. IEEE Des Test Comput 26(6):84–94CrossRefGoogle Scholar
  31. 31.
    Mavroidis I, Papaefstathiou I (2007) Efficient testbench code synthesis for a hardware emulator system. Design, Automation & Test in Europe Conference & Exhibition (DATE 2007), Nice, pp 1–6Google Scholar
  32. 32.
    Banerjee S, Gupta T (2012) Efficient online RTL debugging methodology for logic emulation systems. In: 25th International Conference on VLSI Design, IEEE, Hyderabad, pp 298–303Google Scholar
  33. 33.
    Yingpan Wu, Lixin Yu, Wei Zhuang and Jianyong Wang (2009) A coverage-driven constraint random-based functional verification method of pipeline unit. ACIS International Conference on Computer and Information Science, IEEE, Shanghai, pp 1049–1054Google Scholar
  34. 34.
    Benjamin M, Geist D, Hartman A, Wolfsthal Y, Mas G, Smeets R (1999) A study in coverage-driven test generation. Proceedings of 36th Issue Design Automation Conference, IEEE, New Orleans, pp 970–975Google Scholar
  35. 35.
    Fine S, Ziv A (2003) Coverage directed test generation for functional verification using Bayesian networks. In: Proceedings of Design Automation Conference, IEEE, pp 286–291, 2–6 June 2003Google Scholar
  36. 36.
    Abo-Hammour ZS, Alsmadi OMK, Al-Smadi AM (2011) Frequency-based model order reduction via genetic algorithm approach. In: 7th International Workshop on Systems, Signal Processing and their Applications (WOSSPA), IEEE, Tipaza, pp 91–94Google Scholar
  37. 37.
    Yun I, Carastro LA, Poddar R, Brooke MA, May GS, Hyun K-S, Pyun KE (2000) Extraction of passive device model parameters using genetic algorithms. ETRI J 22(1):38–46CrossRefGoogle Scholar
  38. 38.
    Thirugnanam K, Reena E, Singh M, Kumar P (2014) Mathematical modeling of Li-ion battery using genetic algorithm approach for V2G applications. IEEE Trans Energy Convers 29(2):332–343CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Khaled Salah Mohamed
    • 1
  1. 1.EmulationMentor GraphicsHeliopolisEgypt

Personalised recommendations