New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test Generation

  • Khaled Salah Mohamed
Part of the Analog Circuits and Signal Processing book series (ACSP)


Now, SystemVerilog (SV)/UVM gradually dominate the verification landscape. SV does not support MACROS and the language alone was insufficient to enable widespread adoption of the best-practice verification techniques that inspired its development that is why we need UVM [1, 2]. UVM is a methodology for SoC functional verification that uses TLM standard for communication between blocks and SystemVerilog for its languages, or in other words, it uses SV for creating components and TLM for interconnects between components.


Trends UVM Localization scan-chain methodology GA Test generation SystemVerilog OOP DPI Randomization Constrained Infrastructure Drawbacks Opportunities Metric Watchdog Library 


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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Khaled Salah Mohamed
    • 1
  1. 1.EmulationMentor GraphicsHeliopolisEgypt

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