Analyzing the Trade-off Between Different Memory Cores and Controllers

  • Khaled Salah Mohamed
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

With the move to multicore computing, the demand for memory bandwidth grows with the number of cores. It is predicted that multicore computers will need 1 TBps of memory bandwidth. However, memory device scaling is facing increasing challenges due to the limited number of read and write cycles in flash memories and capacitor-scaling limitations for DRAM cells. Therefore, memory bottleneck is one of the main challenges in modern VLSI design. Microprocessors communicate with memory cores through memory controllers (Fig. 3.1). A detailed figure is shown in Fig. 3.2 [1–6].

Keywords

Trade-off Memory Cores Controllers EMMC SDCARD HMC ONFI ONENAND FLASH RAM BRIDGE JEDEC DDR SSD HDD STANDARD WIDEIO Memristor ReRAM 

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Copyright information

© Springer International Publishing Switzerland 2016

Authors and Affiliations

  • Khaled Salah Mohamed
    • 1
  1. 1.EmulationMentor GraphicsHeliopolisEgypt

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