Abstract
This paper presents a parallel execution model and a core design to run C programs in parallel. The model automatically builds parallel flows of machine instructions from the run trace. It parallelizes instruction fetch, renaming, execution and retirement. Predictor based fetch is replaced by a fetch-decode-and-partly-execute stage able to compute in-order most of the control instructions. Tomasulo’s register renaming is extended to memory with a technique to match consumer/producer pairs. The Reorder Buffer is adapted to parallel retirement. A sum reduction code is used to illustrate the model and to give a short analytical evaluation of its performance potential.
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- 1.
The stack in each section keeps its local variables, e.g. temp on Fig. 5.
- 2.
“Good” model with a 2 K instructions window size, 64 instructions issued per cycle, 256 renaming registers, a branch predictor based on an infinite number of 2-bits counters and a perfect memory aliasing disambiguation.
- 3.
“Perfect” model enhances “good” model: infinite renaming, perfect branch predictor.
- 4.
Hosting core choice to optimize load balancing is out of the scope of this paper.
- 5.
Memory renaming duplicates same address based stack frames. This allows multiple sections to update their local variables in their frames in parallel.
- 6.
In the sum example, the conditional branches are all computed in the fetch stage, allowing the parallelization of the fetch by fetching fastly the fork instructions.
- 7.
Stores update full lines. The loader sets a cleared line and loops to update it successively with t[0] up to t[4]. The full line right padded with zeros is exported to its first consumer, i.e. section 1. Sections 2 and 3 get section 1 cached copy.
- 8.
The oldest section, i.e. the only one with no predecessor, dumps its renamings to the data memory hierarchy (DMH). When it receives a renaming request which misses, it loads from DMH and exports the loaded line.
- 9.
15 cycles is the fetch time of instructions (Fig. 5) 2, 3, 8-10 (5 cycles), the creation time of the forked section (2 cycles), the fetch time of instructions 11-16 (5 cycles) and the retirement of instructions 17-19 (3 cycles).
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Goossens, B., Parello, D., Porada, K., Rahmoune, D. (2015). Toward a Core Design to Distribute an Execution on a Manycore Processor. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2015. Lecture Notes in Computer Science(), vol 9251. Springer, Cham. https://doi.org/10.1007/978-3-319-21909-7_38
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