Abstract
Electrical copper-based through-silicon vias (TSVs) are key elements for vertical connections in 3D interposer chip stacks. For the fabrication of such a chip stack, TSV structures with high aspect ratios (AR) of more than ten are necessary. The following contribution presents several of the key technical challenges associated with TSV fabrications. They include: silicon etching, insulator, barrier- and seed-layer material system deposition by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electrochemical deposition (ECD) of TSV copper fills. Additionally we describe a process for interconnecting and bumping using solder bumps to realize an Si-based interposer as 3D chip stack. To meet these challenges, a process for fabricating high aspect ratio TSVs is presented. The process has been implemented and is shown to result in TSVs with aspect ratios from 10:1 up to 20:1 in thinned 200 μm thick wafer with 10–40 μm in TSV diameter.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
The properties of different stop layers are investigated in Sect. 2.2 of this chapter.
- 2.
Storage of such wafers can be for only a very short time under nitrogen atmosphere or vacuum.
- 3.
Sn60Pb40—liquidus temperature 183 ∘C.
- 4.
Sn97Ag3—liquidus temperature 221 ∘C.
References
J.W. Bartha, J. Greschner, M. Puech, Ph. Maquin, Low temperature etching of Si in high density plasma using \(\mathrm{SF}_{6}/\mathrm{O}_{2}\). Microelectron. Eng. 27(1), 453–456 (1995)
F. Lärmer, A. Schilp, German patent no. DE-4241045, 26.5.1994
S.L. Lai, D. Johnson, R. Westerman, Aspect ratio dependent etching lag reduction in deep silicon etch processes. J. Vac. Sci. Technol. A 24(4), 1283–1288 (2006)
G.S. Hwang, K.P. Giapis, On the origin of the notching effect during etching in uniform high density plasmas. J. Vac. Sci. Technol. B 15(1), 70–87 (1997)
C.-H. Kim, Y.-K. Kim, Prevention method of a notching caused by surface charging in silicon reactive ion etching. J. Micromech. Microeng. 15(2), 358 (2005)
N. Lietaer, P. Storås, L. Breivik, S. Moe, Development of cost-effective high-density through-wafer interconnects for 3D microsystems. J. Micromech. Microeng. 16(6), S29 (2006)
K. Buchanan, The evolution of interconnect technology for silicon integrated circuitry. Proc. of International Conference on Compound Semiconductor Manufacturing - GaAsMAN-TECH 44, 1–3 (2002)
F.E. Rasmussen, J. Frech, M. Heschel, O. Hansen, Fabrication of high aspect ratio through-wafer vias in CMOS wafers for 3-D packaging applications, in Proceedings of the 12th International Conference on Solid-State Sensors, Actuators and Microsystems (Transducers), vol. 2 (IEEE, Piscataway, New Jersey, 2003), pp. 1659–1662
D. Archard, K. Giles, A. Price, S. Burgess, K. Buchanan, Low temperature PECVD of dielectric films for TSV applications, in Electronic Components and Technology Conference (ECTC) (2010), pp. 764–768. ISBN 3-932434-75-7
K. Powell, S. Burgess, T. Wilby, R. Hyndman, J. Callahan, 3D IC process integration challenges and solutions, in International Interconnect Technology Conference (IITC) (IEEE, Piscataway, New Jersey, 2008), pp. 40–42
M. Ritala, M. Leskelä, H.S. Nalwa, Handbook of Thin Film Materials, vol. 1, Chap. 2 (Academic, San Diego, 2001), p. 103
S.K. Kim, J.H. Han, G.H. Kim, C.S. Hwang, Investigation on the growth initiation of Ru thin films by atomic layer deposition. Chem. Mater. 22(9), 2850–2856 (2010)
M. Leskelä, M. Ritala, Atomic layer deposition (ALD): from precursors to thin film structures. Thin Solid Films 409(1), 138–146 (2002)
S.M. George, Atomic layer deposition: an overview. Chem. Rev. 110(1), 111–131 (2009)
D.K. Schroder, Semiconductor Material and Device Characterization (Wiley, New York, 2006)
H. Wojcik, R. Kaltofen, U. Merkel, C. Krien, S. Strehle, J. Gluch, M. Knaut, C. Wenzel, A. Preusse, J.W. Bartha et al., Electrical evaluation of Ru–W (-N), Ru–Ta (-N) and Ru–Mn films as Cu diffusion barriers. Microelectron. Eng. 92, 71–75 (2012)
D. Edelstein, C. Uzoh, C. Cabral Jr., P. DeHaven, P. Buchwalter, A. Simon, E. Cooney, S. Malhotra, D. Klaus, H. Rathore et al., A high performance liner for copper damascene interconnects, in Proceedings of the IEEE 2001 International Interconnect Technology Conference (IEEE, Piscataway, New Jersey, 2001), pp. 9–11
S.M. Aouadi, Y. Zhang, P. Basnyat, S. Stadler, P. Filip, M. Williams, J.N. Hilfiker, N. Singh, J.A. Woollam, Physical and chemical properties of sputter-deposited \(\mathrm{TaC}_{\mathrm{x}}\mathrm{N}_{\mathrm{y}}\) films. J. Phys. Condens. Matter 18(6), 1977 (2006)
M. Knaut, M. Junige, V. Neumann, H. Wojcik, T. Henke, C. Hossbach, A. Hiess, M. Albert, J.W Bartha, Atomic layer deposition for high aspect ratio through silicon vias. Microelectron. Eng. 107, 80–83 (2013)
D. Schmidt, M. Knaut, C. Hossbach, M. Albert, C. Dussarrat, B. Hintze, J.W. Bartha, Atomic layer deposition of Ta–N-based thin films using a tantalum source. J. Electrochem. Soc. 157(6), H638–H642 (2010)
C. Hossbach, S. Teichert, J. Thomas, L. Wilde, H. Wojcik, D. Schmidt, B. Adolphi, M. Bertram, U. Mühle, M. Albert et al., Properties of plasma-enhanced atomic layer deposition-grown tantalum carbonitride thin films. J. Electrochem. Soc. 156(11), H852–H859 (2009)
M. Knaut, M. Junige, M. Albert, J.W. Bartha, In-situ real-time ellipsometric investigations during the atomic layer deposition of ruthenium: a process development from [(ethylcyclopentadienyl)(pyrrolyl) ruthenium] and molecular oxygen. J. Vac. Sci. Technol. A 30(1), 01A151 (2012)
M. Beblo, A. Berktold, U. Bleil, H. Gebrande, B. Grauert, U. Haack, V. Haack, H. Kern, H. Miller, N. Petersen et al., Landolt-Börnstein: numerical data and functional relationships in science and technology-new series, in Landolt-Bornstein: Group 6: Astronomy, vol. 1 (Springer, Berlin, 1982)
L. Guo, A. Radisic, P.C. Searson, Electrodeposition of copper on oxidized ruthenium. J. Electrochem. Soc. 153(12), C840–C847 (2006)
N.S. Marinkovic, M.B. Vukmirovic, R.R. Adzic, Some recent studies in ruthenium electrochemistry and electrocatalysis, in Modern Aspects of Electrochemistry (Springer, New York, 2008), pp. 1–52
T.P. Moffat, M. Walker, P.J. Chen, J.E. Bonevich, W.F. Egelhoff, L. Richter, C. Witt, T. Aaltonen, M. Ritala, M. Leskelä et al., Electrodeposition of Cu on Ru barrier layers for damascene processing. J. Electrochem. Soc. 153(1), C37–C50 (2006)
P.P. Sharma, I.I. Suni, Impedance studies of Ru oxide reduction in sulfuric acid. J. Electrochem. Soc. 158(2), H111–H114 (2011)
Ch. Wenzel, K. Drescher, Applikation flip-chip-bumping, in Interdisziplinäre Methoden in der Aufbau- und Verbindungstechnik, ed. by K.-J. Wolter, S. Wiese (Ddp Goldenbogen, Dresden, Germany, 2003), pp. 157–170. ISBN 3-932434-75-7
Acknowledgements
The authors would like to acknowledge A. Hiess, W. Haas, M. Junige, U. Merkel, K. Richter, A. Jahn, S. Waurenschk, F. Winkler, C. Wenzel from the Institute of Semiconductors and Microsystems, TU Dresden, for their assistance and hard work. Without their research, this project would have been impossible.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Killge, S., Neumann, V., Bartha, J.W. (2016). Copper-Based TSV: Interposer. In: Elfadel, I., Fettweis, G. (eds) 3D Stacked Chips. Springer, Cham. https://doi.org/10.1007/978-3-319-20481-9_2
Download citation
DOI: https://doi.org/10.1007/978-3-319-20481-9_2
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-20480-2
Online ISBN: 978-3-319-20481-9
eBook Packages: EngineeringEngineering (R0)