A Real-Time FPGA-based Solution for Binary Image Thinning

Abstract

This paper presents an optimized FPGA implementation for real-time binary image thinning algorithm. The reference thinning technique is based on iterated comparisons with a set of eight $3\times 3$ binary masks. In the proposed architecture, the processing logic and the internal memory are implemented in a way that the mask matching on each $3\times 18$ image segment can be done in parallel within a single clock cycle. This optimization entails a reduction of more than one order of magnitude in terms of execution cycles with respect to the original algorithm. The algorithm was implemented on an ALTERA Stratix II EP2S30 FPGA. The resource occupation of the thinning block and the dedicated memory controllers is 4 % at 100 MHz clock frequency. The proposed solution produces the output in 0.03 s on a standard PAL $720 \times 576$, allowing for further real-time processing.