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Updating the Energy Model for Future Exascale Systems

Part of the Lecture Notes in Computer Science book series (LNTCS,volume 9137)


The 2008 DARPA Exascale report had as its goal determining if it were possible to achieve 1000X the computational power of the then-emerging peta-scale systems at a system power of no more than 20 MW. The main conclusion was that there was no such path with technology and architectures as projected at that time. Key to this conclusion were architecturally-tailored models as to how projected advances would translate into system performance. This paper introduces a major update to the “heavyweight” (modern server-class multi-core chips) model, with a detailed discussion on the underlying projections as to technology, chip layout and microarchitecture, and system characteristics. The model is run over the same time period as the 2008 model to verify its accuracy.


  • Exascale
  • Energy
  • Technology projection

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  • DOI: 10.1007/978-3-319-20119-1_24
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Fig. 1.
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Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.


  1. 1.

  2. 2.

  3. 3.

  4. 4.

  5. 5.

    e.g. PTM

  6. 6.

    Prior to 2004, constant field Dennard Scaling had C vary with F and \(V_{dd}\) with \(F^2\). After 2004, \(V_{dd}\) has become almost flat, with a much smaller decline with F.


  1. Hpcg: High performance conjugate gradient.

  2. Xeon, February 2015.

  3. Amarasinghe, S., Campbell, D., Carlson, W., Chien, A., Dally, W., Elnohazy, E., Harrison, R., Harrod, W., Hiller, J., Karp, S., Koelbel, C., Koester, D., Kogge, P., Levesque, J., Reed, D., Schreiber, R., Richards, M., Scarpelli, A., Shalf, J., Snavely, A., Sterling, T.: Exascale software study: Software challenges in extreme scale systems (2009)

    Google Scholar 

  4. Brightwell, R., Pedretti, K., Underwood, K.D.: Initial performance evaluation of the cray seastar interconnect. In: Proceedings of the 13th Symposium on High Performance Interconnects, HOTI 2005, pp. 51–57. IEEE Computer Society, Washington, DC (2005)

    Google Scholar 

  5. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th Annual International Symposium on Computer Architecture, ISCA 2000, pp. 83–94. ACM, New York (2000).

  6. Cappello, F., Geist, A., Gropp, B., Kale, L., Kramer, B., Snir, M.: Toward exascale resilience. Int. J. High Perform. Comput. Appl. 23(4), 374–388 (2009).

    CrossRef  Google Scholar 

  7. Dennard, R., Gaensslen, F., Rideout, V., Bassous, E., LeBlanc, A.: Design of ion-implanted mosfet’s with very small physical dimensions. IEEE J. Solid-State Circuits 9(5), 256–268 (1974)

    CrossRef  Google Scholar 

  8. Dongarra, J., Heroux, M.: Toward a new metric for ranking high performance computing systems. Technical report SAND2013-4744, Sandia National Laboratories, June 2013

    Google Scholar 

  9. Elnozahy, M., Bianchini, R., El-Ghazawi, T., Fox, A., Godfrey, F., Hoisie, A., McKinley, K., Melhem, R., Plank, J., Ranganathan, P., Simons, J.: System resilience at extreme scale. Technical report, DARPA Technical report (2009)

    Google Scholar 

  10. Hewlett Packard: Cacti: An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model.

  11. Hsu, J.: When will we have an exascale supercomputer? In: IEEE Spectrum, vol. 52, pp. 13–15. IEEE, January 2015

    Google Scholar 

  12. ITRS: International technology roadmap for semiconductors.

  13. JEDEC: High bandwidth memory (HBM) dram. Technical report, JEDEC Solid State Technology Association, October 2013

    Google Scholar 

  14. Kogge, P.: Tracking the effects of technology and architecture on energy through the top 500, green 500, and graph 500. In: 2012 International Conference on Supercomputing, ISC 2012 (2012)

    Google Scholar 

  15. Kogge, P., Dysart, T.: Using the top500 to trace and project technology and architecture trends. In: Proceedings of the 2011 ACM/IEEE Conference on Supercomputing, SC 2011 (2011)

    Google Scholar 

  16. Kogge, P., Shalf, J.: Exascale computing trends: Adjusting to the new normal for computer architecture. Comput Sci. Eng. 15(6), 16–26 (2013)

    CrossRef  Google Scholar 

  17. Kogge, P.M., Bergman, K., Borkar, S., Campbell, D., Carlson, W., Dally, W., Denneau, M., Franzon, P., Harrod, W., Hill, K., Hiller, J., Karp, S., Keckler, S., Klein, D., Lucas, R., Richards, M., Scarpelli, A., Scott, S., Snavely, A., Sterling, T., Williams, R.S., Yelick, K.: Exascale computing study: Technology challenges in achieving exascale systems. Technical report. CSE 2008–13, University of Notre Dame, September 2008

    Google Scholar 

  18. Kogge, P.M., Resnick, D.R.: Yearly update: Exascale projections for 2013. Technical report SAND2013-9229, University of Notre Dame, Sandia National Laboratories, October 2013

    Google Scholar 

  19. Kogge, P.M., Resnick, D.R.: Yearly update: Exascale projections for 2014. Technical report SAND2014-18651, University of Notre Dame, Sandia National Laboratories, 30 September 2014

    Google Scholar 

  20. Kogge, P., La Fratta, P., Vance, M.: Facing the exascale energy wall. In: 2010 International Workshop on Innovative Architecture for Future Generation High Performance (IWIA), pp. 51–58, January 2010

    Google Scholar 

  21. Li, S., Ahn, J.H., Strong, R.D., Brockman, J.B., Tullsen, D.M., Jouppi, N.P.: Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42, pp. 469–480. ACM, New York (2009).

  22. Micron: Tn-41-01: Calculating memory system power for ddr3.

  23. Moore, G.: Progress in digital integrated electronics. In: 1975 International Electron Devices Meeting, vol. 21, pp. 11–13 (1975)

    Google Scholar 

  24. Moore, G.: Cramming more components onto integrated circuits. Proc. IEEE 86(1), 82–85 (1998)

    CrossRef  Google Scholar 

  25. Navid, R., Chen, E.H., Hossain, M., Leibowitz, B., Ren, J., Chou, C.H., Daly, B., Aleksic, M., Su, B., Li, S., Shirasgaonkar, M., Heaton, F., Zerbe, J., Eble, J.: A 40 gb/s serial link transceiver in 28 nm CMOS technology. IEEE J. Solid-State Circ. 50(4), 814–827 (2015)

    CrossRef  Google Scholar 

  26. Pawlowski, J.T.: 3D stacked memory architectures for multi-core processors. In: 3D Architectures for Semiconductor Integration and Packaging, San Francisco, CA, USA (2012)

    Google Scholar 

  27. Rosenfeld, P., Cooper-Balis, E., Jacob, B.: Dramsim2: A cycle accurate memory system simulator. Comput. Archit. Lett. 10(1), 16–19 (2011)

    CrossRef  Google Scholar 

  28. Rosenfeld, P.: Performance exploration of the hybrid memory cube. Ph.D. thesis, University of Maryland, College Park, MD (2014)

    Google Scholar 

  29. Simon, H.: no exascale for you! an interview with berkeley lab’s horst simon (2013).

  30. Sodani, A.: Race to exascale: Opportunities and challenges, December 2011.

  31. Stevens, R.: On the race to exascale (2013).

  32. Thoziyoor, S.: A comprehensive memory modeling tool for design and analysis of future memory hierarchies. Ph.D. thesis, University of Notre Dame, Notre Dame, IN, USA (2008), aAI3442483

    Google Scholar 

  33. Yokokawa, M., Habata, S., Kawai, S., Ito, H., Tani, K., Miyoshi, H.: Basic design of the earth simulator. In: Fukuda, A., Joe, K., Polychronopoulos, C.D. (eds.) ISHPC 1999. LNCS, vol. 1615, pp. 269–280. Springer, Heidelberg (1999)

    CrossRef  Google Scholar 

  34. Yokokawa, M., Shoji, F., Uno, A., Kurokawa, M., Watanabe, T.: The k computer: Japanese next-generation supercomputer development project. In: Proceedings of the 17th IEEE/ACM International Symposium on Low-power Electronics and Design, ISLPED 2011, pp. 371–372. IEEE Press, Piscataway (2011).

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This material is based upon work supported by the Department of Energy, National Nuclear Security Administration, under Award Number(s) DE-NA0002377, as part of the Center for Shock-Wave Processing of Advanced Reactive Materials, University of Notre Dame. It also builds on work performed under the Sandia National Labs XGC project.

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Correspondence to Peter M. Kogge .

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Kogge, P.M. (2015). Updating the Energy Model for Future Exascale Systems. In: Kunkel, J., Ludwig, T. (eds) High Performance Computing. ISC High Performance 2015. Lecture Notes in Computer Science(), vol 9137. Springer, Cham.

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