Advertisement

Sizing Digital Circuits Using Convex Optimization Techniques

Chapter
  • 614 Downloads

Abstract

This chapter collects recent advances in using convex optimization techniques to perform sizing of digital circuits. Convex optimization techniques provide an undeniably attractive promise: The attained solution is the best available. In order to use convex optimization techniques, the target optimization problem must be modeled using convex functions. The gate sizing problem has been modeled in different ways to enable the use of convex optimization techniques, such as linear programming and geometric programming. Statistical and robust sizing methods are included to reflect the importance of optimization techniques that are aware of variations. Applications of multi-objective optimization techniques that aid designers in evaluating the trade-offs are described.

Keywords

Convex Optimization Stochastic Programming Robust Optimization Digital Circuit Geometric Programming 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Ben-Tal, A., Nemirovski, A.: Robust solutions of linear programming problems contaminated with uncertain data. Math. Program. 88, 411–424 (2000)MathSciNetCrossRefzbMATHGoogle Scholar
  2. 2.
    Berkelaar, M., Jess, J.: Gate sizing in MOS digital circuits with linear programming. In: Proceedings of the Conference on European Design Automation, EURO-DAC ’90, pp. 217–221 (1990)Google Scholar
  3. 3.
    Bertsekas, D.: Nonlinear Programming, edn. Athena Scientific (1999)Google Scholar
  4. 4.
    Bertsimas, D., Brown, D., Caramanis, C.: Theory and applications of robust optimization. SIAM Rev. 53, 464–501 (2011)MathSciNetCrossRefzbMATHGoogle Scholar
  5. 5.
    Boyd, S., Kim, S.J., Vandenberghe, L., Hassibi, A.: A tutorial on geometric programming. Optim. Eng. 8(1), 67–127 (2007)MathSciNetCrossRefzbMATHGoogle Scholar
  6. 6.
    Boyd, S., Vandenberghe, L.: Convex Optimization. Cambridge University Press (2004)Google Scholar
  7. 7.
    Chinnery, D., Keutzer, K.: Linear programming for sizing, vth and vdd assignment. In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. ISLPED ’05. pp. 149–154 (2005). doi: 10.1109/LPE.2005.195505
  8. 8.
    Dyer, M., Stougie, L.: Computational complexity of stochastic programming problems. Math. Program. 106(3), 423–432 (2006)MathSciNetCrossRefzbMATHGoogle Scholar
  9. 9.
    Elmore, W.: The transient response of damped linear networks with particular regard to wideband amplifiers. J. Appl. Phys. 19(1), 55–63 (1948)CrossRefGoogle Scholar
  10. 10.
    Farshidi, A., Rakai, L., Behjat, L., Westwick, D.: Optimal gate sizing using a self-tuning multi-objective framework. Integr. VLSI J. 47(3), 347–355 (2014). (Special issue: VLSI for the new era)Google Scholar
  11. 11.
    Fishburn, J., Dunlop, A.: TILOS: A posynomial programming approach to transistor sizing. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 326–328 (1985)Google Scholar
  12. 12.
    Jeong, K., Kahng, A., Yao, H., Rakai, D.: Revisiting the linear programming framework for leakage power vs. performance optimization. In: Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, pp. 127–134 (2009)Google Scholar
  13. 13.
    Joshi, S., Boyd, S.: An efficient method for large-scale gate sizing. IEEE Trans. Circuits Syst. I: Regul. Pap. 55(9), 2760–2773 (2008)MathSciNetCrossRefGoogle Scholar
  14. 14.
    Kasamsetty, K., Ketkar, M., Sapatnekar., S.: A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]. IEEE Trans. CAD 19(7), 779–788 (2006)Google Scholar
  15. 15.
    Kashfi, F., Hatami, S., Pedram, M.: Multi-objective optimization techniques for VLSI circuits. In: Proceedings of ISQED, pp. 156–163 (2011)Google Scholar
  16. 16.
    Kim, I., de Weck, O.: Adaptive weighted-sum method for bi-objective optimization: Pareto front generation. Struct. Multidiscip. Optim. 29(2), 149–158 (2005)CrossRefGoogle Scholar
  17. 17.
    Luenberger, D.: Theory of Linear and Integer Programming. Springer, Berlin (2003)Google Scholar
  18. 18.
    Nemirovski, A., Juditsky, A., Lan, G., Shapiro, A.: Robust stochastic approximation approach to stochastic programming. SIAM J. Optim. 19(4), 1574–1609 (2009)MathSciNetCrossRefzbMATHGoogle Scholar
  19. 19.
    Nguyen, D., Davare, A., Orshansky, M., Chinnery, D., Thompson, B., Keutzer, K.: Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic ic design]. In: Low Power Electronics and Design, 2003. ISLPED ’03. Proceedings of the 2003 International Symposium on, pp. 158–163 (2003)Google Scholar
  20. 20.
    Orshansky, M., Nassif, S., Boning, D.: Design for Manufacturability and Statistical Design. A Constructive Approach. Springer, Berlin (2007)Google Scholar
  21. 21.
    Rakai, L., Farshidi, A., Westwick, D., Behjat, L.: Variation-aware geometric programming models for the clock network buffer sizing problem. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 33(4), 532–545 (2014)CrossRefGoogle Scholar
  22. 22.
    Sapatnekar, S., Rao, V., Vaidya, P., Kang, S.: An exact solution to the transistor sizing problem for cmos circuits using convex optimization. IEEE Trans. CAD 12, 1621–1634 (1993)CrossRefGoogle Scholar
  23. 23.
    Singh, J., Luo, Z., Sapatnekar, S.: A geometric programming-based worst case gate sizing method incorporating spatial correlation. IEEE Trans. Comput.-Aided Design 27(2), 295–308 (2008)CrossRefGoogle Scholar
  24. 24.
    Singh, J., Nookala, V., Luo, Z., Sapatnekar, S.: Robust gate sizing by geometric programming. In: Proceedings of DAC, pp. 315–320 (2005)Google Scholar
  25. 25.
    Srivastava, A., Sylvester, D., Blaauw, D.: Statistical Analysis and Optimization for VLSI: Timing and Power. Springer, Berlin (2005)Google Scholar
  26. 26.
    Wu, T.H., Davoodi, A., Linderoth, J.: GRIP: Global routing via integer programming. IEEE Trans. CAD 30(1), 72–84 (2011)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing Switzerland 2015

Authors and Affiliations

  1. 1.University of CalgaryCalgaryCanada

Personalised recommendations