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Abstract

This chapter presents a design automation approach that generates automatically error-free area and parasitic optimized layout views of output power stages consisting of multiple power MOSFETs. The tool combines a multitude of constraints associated with DRC, DFM, ESD rules, current density limits, heat distribution, and placement. It uses several optimization steps based on evolutionary computation techniques that precede a bottom-up layout construction of each power MOSFET, its optimization for area and parasitic minimization, and its optimal placement within the output stage power topology network.

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Correspondence to Jorge Guilherme .

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Guilherme, D., Guilherme, J., Horta, N. (2015). Automatic Layout Optimizations for Integrated MOSFET Power Stages. In: Fakhfakh, M., Tlelo-Cuautle, E., Siarry, P. (eds) Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-19872-9_6

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  • DOI: https://doi.org/10.1007/978-3-319-19872-9_6

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-19871-2

  • Online ISBN: 978-3-319-19872-9

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