Skip to main content

Automatic Synthesis of Analog Integrated Circuits Including Efficient Yield Optimization

  • Chapter
  • First Online:
Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design

Abstract

In this chapter, the authors show the main aspects and implications of automatic sizing, including yield. Different strategies for accelerating performance estimation and design space search are addressed. The analog sizing problem is converted into a nonlinear optimization problem, and the design space is explored using metaheuristics based on genetic algorithms. Circuit performance is estimated by electrical simulations, and the generated optimal solution includes yield prediction as a design constraint. The method was applied for the automatic design of a 12-free-variables two-stage amplifier. The resulting sized circuit presented 100 % yield within a 99 % confidence interval, while achieving all the performance specifications in a reasonable processing time. The authors implemented an efficient yield-oriented sizing tool which generates robust solutions, thus increasing the number of first-time-right analog integrated circuit designs.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Ali, S., Wilcock, R., Wilson, P., Brown, A.: Yield model characterization for analog integrated circuit using Pareto-optimal surface. In: 2008 15th IEEE International Conference on Electronics, Circuits and Systems, IEEE, vol. 2, pp. 1163–1166 (2008). doi:10.1109/ICECS.2008.4675065. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=4675065

  2. Allen, P.E., Holberg, D.R.: CMOS Analog Circuit Design, 2nd edn. Oxford University Press, Oxford (2002)

    Google Scholar 

  3. Alpaydin, G., Balkir, S., Dundar, G.: An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7(3), 240–252 (2003). url: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1206446

  4. Antreich, K., Koblitz, R.:Design centering by yield prediction. IEEE Trans. Circ. Syst. 29(2), 88–96 (1982). doi:10.1109/TCS.1982.1085115. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1085115

  5. Barros, M., Guilherme, J., Horta, N.: Analog Circuits and Systems Optimization Based on Evolutionary Computation Techniques. Springer, Berlin (2010)

    Google Scholar 

  6. Beer, M., Spanos, P.: Neural network based Monte Carlo simulation of random processes. In: Proceedings of the ninth …, 1995, pp. 2179–2186 (2005). url: http://www.uncertainty-in-engineering.net/pdf/icossar2005_pdf_017.pdf

  7. Chiang, C.C., Kawa, J.: Design for Manufacturability and Yield for Nano-Scale CMOS. Springer, Netherlands (2007)

    Google Scholar 

  8. De Smedt, B., Gielen, G.: Watson: design space boundary exploration and model generation for analog and RF IC design. IEEE Transa. Comput. Aided Des. Integr. Circ. Syst. 22(2), 213–224 (2003). doi:10.1109/TCAD.2002.806598. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1174096

  9. Director, S., Feldmann, P., Krishna, K.: Statistical integrated circuit design. IEEE J. Solid State Circ. 28(3), 193–202 (1993). doi:10.1109/4.209985. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=209985

  10. Drennan, P.G., McAndrew, C.C.: Understanding MOSFET mismatch for analog design. IEEE J. Solid State Circ. 38(3), 450–456 (2003)

    Article  Google Scholar 

  11. Floudas, C.A., Pardalos, P.M.: Encyclopedia of Optimization, vol. 1. Springer, Berlin (2008)

    Google Scholar 

  12. Gielen, G., Rutenbar, R.A.: Computer-aided design of analog and mixed-signal integrated circuits. Proc. IEEE 88, 1825–1852 (2000)

    Article  Google Scholar 

  13. Gong, F., Basir-Kazeruni, S., He, L., Yu, H.: Stochastic behavioral modeling and analysis for analog/mixed-signal circuits. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 32(1), 24–33 (2013). doi:10.1109/TCAD.2012.2217961. url: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6387696, http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6387696

  14. Herbig, V.: Getting to ‘First Time Right’ in Analog/Mixed-Signal Designs. EE Times, Europe (2008). url: http://www.eetimes.com/document.asp?doc_id=1271601

  15. Hershenson, M.D.M., Boyd, S.P., Lee, T.H.: Optimal design of a CMOS Op-Amp via geometric programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), 1–21 (2001)

    Article  Google Scholar 

  16. Houck, C.R., Joines, J., Kay, M.G.: A genetic algorithm for function optimization: a matlab implementation. NCSU-IE TR 95(09) (1995)

    Google Scholar 

  17. Houck, C.R., Joines, J.A., Kay, M.G.: A Genetic Algorithm for Function Optimization: A Matlab Implementation. Tech. rep., North Carolina State University (1996)

    Google Scholar 

  18. Huss, S.: Analog circuit synthesis: a search for the Holy Grail? In: 2006 IEEE International Symposium on Circuits and Systems, IEEE, pp. 1463–1466. doi:10.1109/ISCAS.2006.1692872. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1692872

  19. Jafari, A., Sadri, S., Zekri, M.: Design optimization of analog integrated circuits by using artificial neural networks. In: 2010 International Conference of Soft Computing and Pattern Recognition, IEEE, pp. 385–388 (2010). doi:10.1109/SOCPAR.2010.5686736, URL http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5686736

  20. Lin, Y., Chen, D., Geiger, R.: Yield enhancement with optimal area allocation for ratio-critical analog circuits. IEEE Trans. Circ. Syst. I: Regul. Pap. 53(3), 534–553 (2006). doi:10.1109/TCSI.2005.858761. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1610852

  21. Liu, B., Wang, Y., Yu, Z., Liu, L., Li, M., Wang, Z., Lu, J., Fernández, F.V.: Analog circuit optimization system based on hybrid evolutionary algorithms. Integr. VLSI J. 42(2), 137–148 (2009). doi:10.1016/j.vlsi.2008.04.003. url: http://linkinghub.elsevier.com/retrieve/pii/S0167926008000126

  22. Liu, B., Fernandez, F.V., Gielen, G.: Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 30(6), 793–805 (2011). doi:10.1109/TCAD.2011.2106850. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5768139

  23. Mandal, P., Visvanathan, V.: CMOS Op-Amp sizing using a geometric programming formulation. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 20(1), 22–38 (2001)

    Article  Google Scholar 

  24. Martins, R.M.F., Lourenço, N.C.C., Horta, N.C.G.: Introduction. In: Generating Analog IC Layouts with LAYGEN II, SpringerBriefs in Applied Sciences and Technology. Springer, Berlin, pp. 1–7 (2013). doi:10.1007/978-3-642-33146-6_1. url: http://dx.doi.org/10.1007/978-3-642-33146-6_1

  25. Mueller-Gritschneder, D., Graeb, H.: Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. In: 2010 Design, Automation & Test in Europe Conference & Exhibition, IEEE, pp. 1088–1093 (2010). doi:10.1109/DATE.2010.5456971. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5456971

  26. Nye, W., Riley, D.C., Sangiovanni-Vincentelli, A., Tits, A.L.: DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. IEEE Tran. Comput. Aided Des. 7(4), 501–519 (1988)

    Google Scholar 

  27. Orshansky, M., Nassif, S.R., Boning, D.: Design for Manufacturability and Statistical Design. Springer, Berlin (2008). url: http://link.springer.com/book/10.1007/978-0-387-69011-7/page/1

  28. Pelgrom MJM, Duinmaijer ACJ, Welbers APG (1989) Matching properties of MOS transistors. IEEE J. Solid State Circ. 24(5), 1433–1439

    Google Scholar 

  29. Phelps, R., Krasnicki, M., Rutenbar, R.A., Carley, L.R., Hellums, J.R.: Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 19(6), 703–717 (2000)

    Article  Google Scholar 

  30. Razavi, B.: Design of Analog CMOS Integrated Circuits, vol 6. McGraw-Hill, New York City. doi:10.1111/j.1151-2916.1994.tb07040.x

  31. Sengupta, M., Saxena, S., Daldoss, L., Kramer, G., Minehane, S.: Application-specific worst case corners using response surfaces and statistical models. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 24(9), 1372–1380 (2005). doi:10.1109/TCAD.2005.852037. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1501902

  32. Singhee, A., Rutenbar. R.: Why Quasi-Monte Carlo is better than Monte Carlo or latin hypercube sampling for statistical circuit analysis. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 29(11), 1763–1776 (2010) doi:10.1109/TCAD.2010.2062750. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5605333

  33. Stefanovic, D., Kayal, M.: Structured Analog CMOS Design, 1st edn., Springer, Berlin (2008)

    Google Scholar 

  34. Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. Oxford University Press, Oxford (1999)

    Google Scholar 

  35. Xu, Y., Hsiung, K.L., Li, X., Pileggi, L.T., Boyd, S.P.: Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 28(5), 623–637 (2009)

    Article  Google Scholar 

  36. Yu, G., Li, P.: Hierarchical analog/mixed-signal circuit optimization under process variations and tuning. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 30(2), 313–317 (2011). doi:10.1109/TCAD.2010.2071250. url: http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5689353

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Alessandro G. Girardi .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Severo, L.C., Kepler, F.N., Girardi, A.G. (2015). Automatic Synthesis of Analog Integrated Circuits Including Efficient Yield Optimization. In: Fakhfakh, M., Tlelo-Cuautle, E., Siarry, P. (eds) Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-19872-9_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-19872-9_2

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-19871-2

  • Online ISBN: 978-3-319-19872-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics