Skip to main content
SpringerLink
Log in

Automated System-Level Design for Reliability: RF Front-End Application

  • Chapter
  • First Online:
Book cover Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design

Abstract

Reliability is an important issue for circuits in critical applications such as military, aerospace, energy, and biomedical engineering. With the rise in the failure rate in nanometer CMOS, reliability has become critical in recent years. Existing design methodologies consider classical criteria such as area, speed, and power consumption. They are often implemented using postsynthesis reliability analysis and simulation tools. This chapter proposes an automated system design for reliability methodology. While accounting for a circuit’s reliability in the early design stages, the proposed methodology is capable of identifying an RF front-end optimal design considering reliability as a criterion.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Abbreviations

\( G_{\text{RF}} \) :

Total gain

\( F_{\text{RF}} \) :

Total noise

\( {\text{IP}}3_{\text{RF}} \) :

Total linearity

\( S_{11} \) :

Input matching

\( V_{\text{DD}} \) :

Supply voltage

\( f_{\text{LO}} \) :

Local oscillator frequency

\( G_{\text{LNA}} \) :

LNA gain specification

\( {\text{NF}}_{\text{LNA}} \) :

LNA noise specification

\( {\text{IP}}3_{\text{LNA}} \) :

LNA linearity specification

\( G_{\text{PGA}} \) :

PGA gain specification

\( V_{{n{\text{PGA}}}}^{{2^{ - } }} \) :

PGA noise specification

\( {\text{IP}}3_{\text{PGA}} \) :

PGA linearity specification

\( \Phi \) :

A general system-level specification where \( \Phi \in \left[ {G_{\text{RF}} ,F_{\text{RF}} ,{\text{IP}}3_{\text{RF}} ,S_{11} ,V_{\text{DD}} ,\,f_{\text{LO}} } \right] \) at chapter’s design example

\( \psi \) :

A general building block characteristic where \( \psi \in \left[ {G_{\text{LNA}} ,{\text{NF}}_{\text{LNA}} ,{\text{IP}}3_{\text{LNA}} ,G_{\text{PGA}} ,V_{{n{\text{PGA}}}}^{{2^{ - } }} ,{\text{IP}}3_{\text{PGA}} } \right] \) at chapter’s design example

References

  1. Tu, R.H., Rosenbaum, E., Chan, W.Y., Li, C.C., Minami, E., Quader, K., Ko, P.K., Hu, C.: Berkeley reliability tools-BERT. Technical Report. Electronics Research Lab, Dec 1991 (1992)

    Google Scholar 

  2. Oshiro L, Diego S (1995) A Design Reliability Methodology for CMOS. In: Proc. of Int. Integrated Reliability Workshop, 619, pp. 34–39

    Google Scholar 

  3. ITRS (2011) Modeling and simulation. Technical Report, International Roadmap for Semiconductors

    Google Scholar 

  4. Maricau, E., Gielen, G.: Computer-aided analog circuit design for reliability in nanometer CMOS. IEEE Trans. Emerg. Select Top. Circ. Syst. 1(1), 50–58 (2011)

    Article  Google Scholar 

  5. Maricau, E., De Wit, P., Gielen, G.: An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications. Microelectron. Reliab. 48(8–9), 1576–1580 (2008). doi:10.1016/j.microrel.2008.06.016

    Article  Google Scholar 

  6. Ferreira, P.M, Petit, H., Naviner, J.F.: AMS and RF design for reliability methodology. In: Proceedings of IEEE ISCAS, IEEE, pp. 3657–3660 (2010)

    Google Scholar 

  7. Ferreira, P.M., Petit, H., Naviner, J.F.: A new synthesis methodology for reliable RF front-end design. In: Proceedings of IEEE ISCAS, pp. 1–4 (2011)

    Google Scholar 

  8. Ferreira, P.M., Petit, H., Naviner, J.F.: A synthesis methodology for AMS/RF circuit reliability: application to a DCO design. Microelectron. Reliab. 51(4), 765–772 (2010). doi:10.1016/j.microrel.2010.11.002

    Article  MATH  Google Scholar 

  9. Ferreira, P.M., Petit, H., Naviner, J.F.: WLAN/WiMAX RF front-end reliability analysis. In: IEEE Proceedings of EAMTA 2010, IEEE, pp. 46–49 (2010)

    Google Scholar 

  10. Cai, H., Petit, H., Naviner, J.F.: A hierarchical reliability simulation methodology for AMS integrated circuits and systems. J. Low Power Electron. 8(5), 697–705 (2012). doi:10.1166/jolpe.2012.1228

    Article  Google Scholar 

  11. Ferreira, P.M., Cai, H., Naviner, L.: Reliability aware AMS/RF performance optimization. In: Fakhfakh, M., Tlelo-Cuautle, E., Fino, M.H.S. (eds.) Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design. IGI-Global, Hershey (2014)

    Google Scholar 

  12. Mutlu, A.A., Rahman, M., Member, S.: Statistical methods for the estimation of process variation effects on circuit operation. IEEE Trans. Electron. Packag. Manuf. 28(4), 364–375 (2005)

    Article  MATH  Google Scholar 

  13. Ramdani, M., Sicard, E., Boyer, A., Dhia, S.B., Whalen, J.J., Hubing, T.H., Coenen, M., Wada, O.: The electromagnetic compatibility of integrated circuits—past, present, and future. IEEE Trans. Electromagn. Compat. 51(1), 78–100 (2009)

    Article  Google Scholar 

  14. Rosa, J.M.D.L., Castro-López, R., Morgado, A., Becerra-Alvarez, E.C., Ro, R.D., Fernández, F.V., Pérez-Verdú, B.: Adaptive CMOS analog circuits for 4G mobile terminals—review and state-of-the-art survey. Microelectron. J. 40(1), 156–176 (2009). doi:10.1016/j.mejo.2008.07.001

    Article  Google Scholar 

  15. White, M., Chen, Y.: Scaled CMOS technology reliability users guide. JPL Publication, 08–14 Mar 2008

    Google Scholar 

  16. Stathis, J.H.: Percolation models for gate oxide breakdown. J. Appl. Phys. 86(10), 5757 (1999). doi:10.1063/1.371590

    Article  Google Scholar 

  17. Liu, B., Wang, Y., Yu, Z., Liu, L., Li, M., Wang, Z., Lu, J., Fernandez, F.: Analog circuit optimization system based on hybrid evolutionary algorithms. Integr. VLSI J. 42(2), 137–148 (2009). doi:10.1016/j.vlsi.2008.04.003

    Article  Google Scholar 

  18. Tugui, C., Benassi, R., Apostol, S., Benabes, P.: Efficient optimization methodology for CT functions based on a modified Bayesian Kriging Approach. In: IEEE Proceedings of International Conference on Electronics Circuits and Systems, pp. 456–459 (2012)

    Google Scholar 

  19. Huard, V., Parthasarathy, C.R., Bravaix, A., Hugel, T., Guérin, C., Vincent, E.: Design-in-reliability approach for NBTI and hot-carrier degradations in advanced nodes. IEEE Trans. Dev. Mater. Reliab. 7(4), 558–570 (2007)

    Article  Google Scholar 

  20. Parthasarathy, C.R., Bravaix, A., Guérin, C., Monnet, J.: Design-in reliability for 90–65 nm CMOS nodes submitted to hot-carriers and NBTI degradation. In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, pp. 191–200. Springer, Berlin. doi:10.1007/978-3-540-74442-9_19 (2007)

  21. Ruberto, M., Degani, O., Wail, S., Tendler, A., Fridman, A., Goltman, G.: A reliability-aware RF power amplifier design for CMOS radio chip integration. In: Proceedings of IEEE International Reliability Physics Symposium, Phoenix, pp. 536–540 (2008)

    Google Scholar 

  22. Quemerais, T., Moquillon, L., Huard, V., Fournier, J.M., Benech, P., Corrao, N.: DC hot carrier stress effect on CMOS 65 nm 60 GHz power amplifiers. In: Proceedings of IEEE Radio Frequency Integrated Circuits Symposium, vol. 31(9), pp. 351–354. doi:10.1109/RFIC.2010.5477310 (2010)

  23. Wunderle, B., Michel, B.: Lifetime modelling for microsystems integration: from nano to systems. Microsyst. Technol. 15(6), 799–812 (2009). doi:10.1007/s00542-009-0860-z

    Article  Google Scholar 

  24. Li, X., Qin, J., Huang, B., Zhang, X., Bernstein, J.B., Member, S.: A new SPICE reliability simulation method for deep submicrometer CMOS VLSI circuits. IEEE Trans. Dev. Mater. Reliab. 6(2), 247–257 (2006)

    Article  Google Scholar 

  25. Wang, V., Agarwal, K., Nassif, S.R., Nowka, K.J., Markovic, D.: A simplified design model for random process variability. IEEE Trans. Semicond. Manuf. 22(1), 12–21 (2008). doi:10.1109/TSM.2008.2011630

    Article  Google Scholar 

  26. Bernstein, J.B., Gurfinke, M., Li, X., Walters, J., Shapira, Y., Talmor, M.: Electronic circuit reliability modeling. Microelectron Reliab 46(12), 1957–1979 (2006). doi:10.1016/j.microrel.2005.12.004

    Article  Google Scholar 

  27. Yuan, J., Tang, H.: CMOS RF design for reliability using adaptive gate-source biasing. IEEE Trans. Electron. Dev. 55(9), 2348–2353 (2008). doi:10.1109/TED.2008.928024

    Article  Google Scholar 

  28. Maricau, E., Gielen, G.: Efficient variability-aware NBTI and hot carrier circuit reliability analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12), 1884–1893 (2010)

    Article  Google Scholar 

  29. Pan, X., Graeb, H.: Reliability analysis of analog circuits using quadratic lifetime worst-case distance prediction. In: IEEE Proceedings of Custom Integrated Circuits, pp. 1–4 (2010)

    Google Scholar 

  30. Osborne, M.J.: An Introduction to Game Theory. Oxford University Press, Oxford (2003). doi:10.1360/99ws0111

    Google Scholar 

  31. Gu, Q.: RF System Design of Transceivers for Wireless Communications. Springer, New York (2006)

    Google Scholar 

  32. Xu, Y., Hsiung, K.L., Li, X., Pileggi, L.T., Boyd, S.P.: Regular analog/RF integrated circuits design using optimization with recourse including ellipsoidal uncertainty. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5), 623–637 (2009). doi:10.1109/TCAD.2009.2013996

    Article  Google Scholar 

  33. Li, X., Gopalakrishnan, P., Xu, Y., Pileggi, L.T.: Robust analog/RF circuit design with projection-based performance modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1), 2–15 (2007). doi:10.1109/TCAD.2006.882513

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronic Systems, GeePs, UMR CNRS 8507, CentraleSupélec - Campus Gif, Gif-sur-Yvette, 91192, France

    Pietro Maris Ferreira & Philippe Benabes

  2. Department of Electrical and Computer Engineering, California State University Northridge, Northridge, CA, 91330, USA

    Jack Ou

  3. IEMN, UMR CNRS 8520, Department of DHS, Lille-1 University, Lille, France

    Christophe Gaquière

Authors
  1. Pietro Maris Ferreira
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jack Ou
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Christophe Gaquière
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Philippe Benabes
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Pietro Maris Ferreira .

Editor information

Editors and Affiliations

  1. Department of Electronics, ENET'Com, University of Sfax, Sfax, Tunisia

    Mourad Fakhfakh

  2. Dept. of Electronics, INAOE, Tonantzintla, Puebla, Mexico

    Esteban Tlelo-Cuautle

  3. Laboratory LiSSi (EA 3956), Université Paris-Est Créteil, Vitry-sur-Seine, France

    Patrick Siarry

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Ferreira, P.M., Ou, J., Gaquière, C., Benabes, P. (2015). Automated System-Level Design for Reliability: RF Front-End Application. In: Fakhfakh, M., Tlelo-Cuautle, E., Siarry, P. (eds) Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-19872-9_13

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-19872-9_13

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-19871-2

  • Online ISBN: 978-3-319-19872-9

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation