Skip to main content

An Overview of Three-Dimensional Integration and FPGAs

  • Chapter
  • First Online:
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 350))

Abstract

The capabilities of many digital electronic devices are strongly linked to Moore’s law: processing speed, memory and functional capacity and even the number and size of pixels in digital cameras. All of these are improving at roughly exponential rates as well. This exponential improvement has dramatically enhanced the impact of digital electronics in nearly every segment of the semiconductor industry, and is a driving force of technological and social change in the late 20th and early 21st centuries. This chapter discusses the historical evolution of semiconductor industry from 2D CMOS based technologies to today’s three-dimensional (3D) integrated circuits using 3D vertical interconnects. Our main focus in this book is to explain the need and the development of tools and technologies that supports the utilization this emerging technology to improve the performance and manufacturability of high density Field Programmable Gate Arrays (FPGAs).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. G. Moore, Cramming more components onto integrated circuits. Proc. IEEE 86(2), 82–85 (1998)

    Article  Google Scholar 

  2. SIA: Semiconductor Industries Association, The International Technology Roadmap for Semiconductor (SEMATECH, Austin, TX, 2009)

    Google Scholar 

  3. P. Garrou, C. Bower, P. Ramm, Handbook of 3D Integration (Wiley-VCH, 2008). ISBN: 978-3-527-32034-9

    Google Scholar 

  4. V.F. Pavlidis, E.G Friedman, Three-Dimensional Integrated Circuit Design (Morgen Kaufmann, 2009). ISBN: 978-0-12-374343-5

    Google Scholar 

  5. Altera, Stratix V device overview (2013), www.altera.com

  6. Xilinx Inc, Two flows for partial reconfiguration: module based or difference based (2004), http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf

  7. J. Rose, R. Francis, D. Lewis, P. Chow, Architecture of field-programmable gate arrays: the effect of logic functionality on area efficiency. IEEE JSSC 25(5), 1217–1225 (1990)

    Google Scholar 

  8. V. Betz, J. Rose, How much logic should go in an FPGA logic block?. IEEE Des. Test Comput. 15(1), 10–15 (1998)

    Google Scholar 

  9. E. Ahmed, J. Rose, The Effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(3), 288–298 (2004)

    Google Scholar 

  10. M. Lin, A.E. Gamal, Y.-C. Lu, S. Wong, Performance benefits of monolithically stacked 3D FPGA, in Proceedings of the 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, Monterey, California, USA, 22–24 Feb 2006, pp. 113–122

    Google Scholar 

  11. I. Kuon, J. Rose, Measuring the gap between FPGAs and ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), 203–215 (2007). http://dx.doi.org/10.1109/TCAD.2006.884574, IEEE Council on Electronic Design Automation

  12. F. Li, D. Chen, L. He, J. Cong, Architecture evaluation for power-efficient FPGAs, in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Array, Nov 2003, pp. 175–184

    Google Scholar 

  13. A. DeHon, Reconfigurable Architectures for General-Purpose Computing, Ph.D. dissertation, Department of Elect Engg and Computer Science, Massachusetts Institute of Technology, 1996

    Google Scholar 

  14. C. Ababei P. Maidee and K. Bazargan, Exploring potential benefits of 3D FPGA integration, in Field Programmable Logic and Application, vol. 3203 (Springer, Berlin, Germany, 2004), pp. 874–880

    Google Scholar 

  15. K. Siozios, A. Bartzas, D. Soudris. Architecture level exploration of alternative schmes targeting 3D FPGAs: a software supported methodology. Int. J. Reconfig. Comput. 2008 (2008)

    Google Scholar 

  16. K. Siozios, V.F. Pavlidis, D. Soudris, A Novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric. ACM Trans. Reconfig. Technol. Syst. 5(1) (2012)

    Google Scholar 

  17. A. DeHon, Unifying mesh- and tree-based programmable interconnect. IEEE Trans. Very Large Scale Integr. VLSI Syst. 12(10), 1051–1065 (2004)

    Article  Google Scholar 

  18. A. DeHon, R. Rubin, Design of FPGA interconnect for multilevel metallization. IEEE Trans. Very Large Scale Integr. VLSI Syst. 12(10), 1038–1050 (2004)

    Article  Google Scholar 

  19. Z. Marrakchi, H. Mrabet, C. Masson, H. Mehrez, Mesh of tree: unifying mesh and MFPGA for better device performances, in NOCS-2007, pp. 243–252 (2007)

    Google Scholar 

  20. Z. Marrakchi, H. Mrabet, U. Farooq, H. Mehrez, FPGA interconnect topologies exploration. Int. J. Reconfig. Comput. 2009 (2009)

    Google Scholar 

  21. S. Gupta, M. Hilbert, S. Hong, R. Patti, Techniques for Producing 3D ICs with High-Density Interconnect (Tezzaron Semiconductor, Naperville, IL, 2005)

    Google Scholar 

  22. R. Patti, Advances in 3D memory and logic devices, in IMAPS International Conference on Device Packaging (TAI3, Scottsdale, AZ, March 2010)

    Google Scholar 

  23. B. Landman, R. Russo, On a pin versus block relationship for partitions of logic graphs. IEEE Trans. Comput. 20(12), 1469–1479 (1971)

    Article  Google Scholar 

  24. J. Pistorius, M. Hutton, Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation, in Proceedings of the International Workshop on System Level Interconnect Prediction (Monterey, Calif, USA, April 2003), pp. 31–38

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Vinod Pangracious .

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Pangracious, V., Marrakchi, Z., Mehrez, H. (2015). An Overview of Three-Dimensional Integration and FPGAs. In: Three-Dimensional Design Methodologies for Tree-based FPGA Architecture. Lecture Notes in Electrical Engineering, vol 350. Springer, Cham. https://doi.org/10.1007/978-3-319-19174-4_1

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-19174-4_1

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-19173-7

  • Online ISBN: 978-3-319-19174-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics