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Dream Chip Project at ASET

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Three-Dimensional Integration of Semiconductors

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Abstract

Chapter 9 introduces the results of Japanese national research and development (R&D) initiative of 3D integration technology using through-silicon via (TSV) over the 5-year period from 2008 to 2012. Association of Super-Advanced Electronics Technologies (ASET) conducted the “Development on Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology Project,” and it was managed by the NEDO organization. The development subjects consisted of thermal management/chip-stacking technology, thin wafer technology, and 3D integration technology, ultrawide bus 3D-SiP, mixed signal (digital -analog) 3D, and heterogeneous 3D technology.

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References

  1. ASET (2013) Presentation slide dream-chip project by ASET (final result). March 8, http://aset.la.coocan.jp/english/e-kenkyu/Dream_Chip_Pj_Final-Results_ASET.pdf. Accessed 12 Jul 2014

  2. Kada M (2014) R & D overview of 3D integration technology using TSV worldwide and in Japan. 2014 ECS and SMEQ joint international meeting (October 5–10)

    Google Scholar 

  3. Kohara S et al (2012) Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration. Presented at 3D system integration conference (3DIC), 31 January–02 February 2012) Osaka, Japan

    Google Scholar 

  4. Kohara S et al (2012) Thermal cycle tests and observation of fine-pitch IMC bonding in 3D chip stack. Presented at microjoining and assembly technology in electronics (MATE) conference, (31 January–1 February 2012), Yokohama, Japan (in Japanese)

    Google Scholar 

  5. Yoo JH et al (2010) Analysis of electromigration for cu pillar bump in flip chip package. Presented at electronics packaging technology conference (EPTC), (08–10 December 2010) Singapore

    Google Scholar 

  6. Wright SL et al (2006) Characterization of micro-bumpC4 interconnects for Si-carrier SOP applications. Presented at electronic components and technology conference (ECTC), (31 May–2 June 2006) San Diego

    Google Scholar 

  7. Lu M et al (2012) Effect of joule heating on electromigration reliability of Pb-free interconnect. Presented at electronic components and technology conference (ECTC), (29 May–01 Jun 2012), San Diego

    Google Scholar 

  8. Sueoka K et al (2013) High precision bonding for fine-pitch interconnection. Presented at international conference on electronics packaging (ICEP), (10–12 April 2013), Osaka, Japan

    Google Scholar 

  9. Sueoka K et al (2011) Joining method for thin si chips. Presented at micro electronics symposium (MES), (8–9 September 2011), Osaka, Japan (in Japanese)

    Google Scholar 

  10. Horibe A et al (2011) High density 3D TSV chip integration process. Presented at international conference on electronics packaging (ICEP), (13–15 April 2011), Nara, Japan

    Google Scholar 

  11. Kitaichi K et al (2013) 3D package assembly development with the use of the dicing tape having NCF layer. Presented at international conference on electronics packaging (ICEP), (10–12 April 2013), Osaka, Japan

    Google Scholar 

  12. Sueoka K et al (2011) TSV diagnostics by X-ray microscopy. Presented at electronics packaging technology conference (EPTC), (07–09 December 2011), Singapore

    Google Scholar 

  13. Matsumoto K et al (2011) Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack. Presented at semiconductor thermal measurement and management symposium (SEMI-THERM) (20–24 March 2011), San Jose

    Google Scholar 

  14. Matsumoto K et al (2012) Experimental thermal resistance evaluation of a three-dimensional (3D) chip stack, including the transient measurements. Presented at semiconductor thermal measurement and management Symposium (SEMI-THERM), (18–22 March 2012), San Jose

    Google Scholar 

  15. Yamada F et al (2013) Cooling strategy and structure of 3D integrated image sensor for auto-mobile application. Presented at international conference on electronics packaging (ICEP), (10–12 April 2013), Osaka, Japan

    Google Scholar 

  16. Matsumoto K et al (2013) Thermal design guidelines for a three-dimensional (3D) chip stack, including cooling solutions. Presented at semiconductor thermal measurement and management symposium (SEMI-THERM), (17–21 March 2013), San Jose

    Google Scholar 

  17. Matsumoto K et al (2013) Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack. Presented at 3D system integration conference (3DIC), (02–04 October 2013), San Francisco

    Google Scholar 

  18. Suekawa S et al (2013) A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor. ISSCC 27.4, 484–486

    Google Scholar 

  19. Kim D-W et al (2013) Development of 3D Through Silicon Stack (TSS) assembly for wide IO memory to logic devices integration. Electron Compon Technol Conf 77–80

    Google Scholar 

  20. Graham S (2014) Hybrid Memory Cube: your new standard for memory performance. ICEP 821–825

    Google Scholar 

  21. Lee DU et al (2014) A 1.2V 8 Gb 8-channel 128 GB/s High-Bandwidth Memory (HBM) stacked DRAM with effective microbump I/O test methods using 29 nm process and TSV. ISSCC 25.2, 432–433

    Google Scholar 

  22. Shimamoto H et al (2014) Study for CMOS device characteristics affected by ultra thin wafer thinning. IEEE ICSJ Symp 22–24

    Google Scholar 

  23. www.disco.co.jp/eg/solution/library/stresslief.html

  24. John R-S-E et al (2013) Low cost, room temperature debondable spin-on temporary bonding solution: a key enable for 2.5/3D IC packaging. Electron Compon Technol Conf 107–112

    Google Scholar 

  25. Jourdain A et al (2013) Integration and manufacturing aspects of moving from WaferBOND HT-10.10 to ZoneBOND material in temporary wafer bonding and debonding for 3D applications. Electron Compon Technol Conf 113–117

    Google Scholar 

  26. Kubo A et al (2014) Development of new concept thermoplastic temporary adhesive for 3D-IC integration. Electron Compon Technol Conf 899–905

    Google Scholar 

  27. www.disco.co.jp/eg/apexp/grinder/ncg.html

  28. www.disco.co.jp/eg/solution/library/dbg.html

  29. www.disco.co.jp/eg/solution/library/stealth.html

  30. Lee K et al (2013) Degradation of memory retention characteristics in DRAM chip by Si thinning for 3-D integration. IEEE Electron Device Lett 34(8):1038–1040

    Google Scholar 

  31. Kim YS et al (2014) Ultra thinning down to 4-um using 300-mm wafer proven by 40-nm node 2 Gb DRAM for 3D multi-stack WOW applications. VLSI Symp Technol Dig 3.2, 26–27

    Google Scholar 

  32. Bea J et al (2011) Evaluation of Cu contamination at backside surface of thinned wafer in 3-D integration by transient-capacitance measurement. IEEE Electron Device Lett 32(1):66–68

    Google Scholar 

  33. www.disco.co.jp/eg/solution/apexp/polisher/gettering.html

  34. Murugesan M et al (2013) Mechanical characteristics of thin dies/wafers in three-dimensional large-scale integrated systems. 24th SEMI-Advanced Semiconductor Manufacturing Conference, 66–69

    Google Scholar 

  35. Murugesan M et al (2010) Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias. IEDM Technol Dig 2.3.1

    Google Scholar 

  36. Shimamoto H (2015) Thin wafer bending strength measurement standardization. 21th Mate 199–202

    Google Scholar 

  37. Ryu S et al (2012) Effect of thermal stresses on carrier mobility and keep-out zone around through-silicon vias for 3-D integration. IEEE Trans Device Mater Reliab 12:255–262

    Article  CAS  Google Scholar 

  38. Mercha A et al (2010) Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance. International Electron Devices Meeting, P.2.2.1

    Google Scholar 

  39. Takahashi K et al (2001) Current status of research and development for three-dimensional chip stack technology. Jpn J Appl Phys 40:3032–3037

    Article  CAS  Google Scholar 

  40. Lee DU et al (2014) An Exact Measurement and Repair Circuit of TSV Connection for 128 GB/s High-Bandwidth Memory(HBM) Stacked DRAM. In: Proceeding of VLSI-Circuit, pp 27–28

    Google Scholar 

  41. Jang DM et al (2007) Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV). In: Proceeding of 57th ECTC, pp 847–852

    Google Scholar 

  42. Ikeda H et al (2012) Development of TSV/3D Memory+ Logic SiP with 4k-IO Interconnects. In: Proceeding of ICEP-IAAC, pp 60–76

    Google Scholar 

  43. Takatani H et al (2012) PDN impedance and noise simulation of 3D SiP with a widebus structure. IEEE electronic components and technology conference, pp 673–677

    Google Scholar 

  44. Takaya Satoshi et al (2013) A 100 GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. In: Proceeding of ISSCC, pp 434–436

    Google Scholar 

  45. Rebeiz M G, Entesari K, Reines I C, Park S, El-Tanani MA, Grichener A., and Brown R. A. (2009) Tuning into RF MEMS. IEEE Microwave Magazine 55–72, Oct

    Google Scholar 

  46. Entesari K, Rebeiz GM (2005) A differential 4-bit 6.5–10-GHz RF MEMS tunable filter. IEEE Trans Microw Theory Tech 53(3):1103–1110

    Article  Google Scholar 

  47. Mi X, Kawano Y, Toyoda O, Suzuki T, Ueda S, Hirose T, Joshin K (2010) Miniaturized microwave tunable bandpass filters on high-k LTCC. In: Proceeding of APMC. pp 139–142

    Google Scholar 

  48. Inoue H, Mi X, Fujiwara T, Toyoda O, Ueda S, Nakazawa F (2012) A novel tunable filter enabling both center frequency and bandwidth tunability. In: Proceeding of 42nd EUMC, pp 269–272

    Google Scholar 

  49. Mi X, Takahashi T, Ueda S (2008) Integrated passives on LTCC for achieving chip-sized-modules. In: Proceeding of 38th EUMC. pp 607–610

    Google Scholar 

  50. Rebeiz GM (2003) RF MEMS theory, design, and technology. New Jersey: Wiley

    Google Scholar 

  51. Majumder S, Lampen J, Morrison R, Maciel J (2003) A packaged, high-lifetime ohmic MEMS RF switch. IEEE MTT-S International Microwave Symposium Digest 1935–1938 (Jun)

    Google Scholar 

  52. Newman HS, Ebel JL, Judy D, Maciel J (2008) Lifetime measurements on a high-reliability RF-MEMS contact switch. IEEE Microw Wirel Compon Lett 18(2):100–102 (Feb)

    Google Scholar 

  53. Guerre R, Drechsler U, Bhattacharyya D, Rantankari P, Stutz R, Wright RV, Milosavljevic ZD, Vaha-Heokkila T, Kirby PB, Despont M (2010) Wafer-level transfer technology for PZT-based RF MEMS switches. J Microelectromech Syst 19(3):548–560 (Jun)

    Article  Google Scholar 

  54. Pulskamp JS, Judy DC, Polcawich RG, Kaul R, Chandrahalim H, Bhave SA (2006) PZT actuated seesaw SPDT RF MEMS switch. J Phys: Conf Ser 34(304):304–309

    Google Scholar 

  55. Nakatani T, Katsuki T, Okuda H, Toyoda O, Ueda S, Nakazawa F (2011) PZT actuated reliable RF-MEMS switch using single crystal silicon asymmetric beam. In: Proceeding of IEEE Asia pacific microwave conference

    Google Scholar 

  56. Nakazawa F, Shimanouchi T, Nakatani T, Katsuki T, Okuda H, Toyoda O, Ueda S (2011) Effect of frequency in the 3D integration of a PZT-actuated MEMS switch using a single crystal silicon asymmetric beam” In: Proceeding of 3DIC

    Google Scholar 

  57. Nakazawa F, Mi S, Shimanouchi T, Nakatani T, Katsuki T, Okuda H, Toyoda O, Ueda S (2012) 3D heterogeneous integration using MEMS devices for RF applications. In: Proceeding of MRS spring conference

    Google Scholar 

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Acknowledgments

Part of this work was entrusted by NEDO “Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology” project that is based on the Japanese government’s METI “IT Innovation Program.”

Author information

Authors and Affiliations

  1. The National Institution of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan

    Morihiro Kada

  2. Advanced Industrial Science and Technology (AIST), Ibaraki, Japan

    Haruo Shimamoto

  3. Lapis Semiconductor, Kanagawa, Japan

    Harufumi Kobayashi

  4. IBM Research, Tokyo, Japan

    Dr. Fumiaki Yamada

  5. Micron Memory Japan, Kanagawa, Japan

    Shiro Uchiyama

  6. Hitachi Ltd., Tokyo, Japan

    Dr. Kenichi Takeda & Kenichi Osada

  7. DENSO Corp., Aichi, Japan

    Tadashi Kamada

  8. FUJITSU LABORATORIES LTD., Kanagawa, Japan

    Fumihiko Nakazawa

Authors
  1. Morihiro Kada
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  2. Harufumi Kobayashi
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  3. Dr. Fumiaki Yamada
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  4. Haruo Shimamoto
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  5. Shiro Uchiyama
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  6. Dr. Kenichi Takeda
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  7. Kenichi Osada
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  8. Tadashi Kamada
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  9. Fumihiko Nakazawa
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Corresponding author

Correspondence to Morihiro Kada .

Editor information

Editors and Affiliations

  1. Department of Chemical Engineering, Osaka Prefecture University, Osaka, Japan

    Kazuo Kondo

  2. AIST , Tsukuba, Ibaraki, Japan

    Morihiro Kada

  3. Toshiba Corporation, Oita, Japan

    Kenji Takahashi

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Kada, M. et al. (2015). Dream Chip Project at ASET. In: Kondo, K., Kada, M., Takahashi, K. (eds) Three-Dimensional Integration of Semiconductors. Springer, Cham. https://doi.org/10.1007/978-3-319-18675-7_9

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