1 General Design and Gain of Amp5

With the T1 & T3 RIAA network included, the Amp5 gain stage must lift the output level of Amps 3 or 4 to a nominal output level of 0 dBu or 0 dBV or +6 dBu at 1 kHz, depending on ones own needs. Hence, we set on a nominal 0 dBV/1 kHz based gain of 6.25 here. In addition, this gain stage should be capable to drive a 1:1 output transformer. Generally, the overload margin should not be lost out of sight. However, it becomes less dramatic: with the +20 dB goal at the input we would get 10Vrms at the output, which is much smaller than the maximal possible 17.2Vrms.

Figures 6.1 and 6.2 show the solution. It follows the basic design of Amp4 with only one further gain stage to get an un-balanced output via OP5. This stage produces the same output level, but less good overload margin. P1 sets the gain of Amp5. Of course, to get higher gains R3 could be chosen smaller. The gain Gamp5 of such an amplifying stage becomes:

$$ \begin{aligned} {\text{G}}_{{\text{amp5}}} & = {\text{G}}_{{\text{1st}}} {\text{G}}_{{\text{2nd}}} \\ & = \left( {1 + \frac{{\text{R4}} + {\text{R5}}}{{\text{RG}}}} \right)\left( {\frac{{\text{R10}}}{{\text{R6}}} + \frac{{\text{R13}}}{{\text{R9}}}} \right) \\ {\text{RG}} & = {\text{P1}} + {\text{R3}} \\ \end{aligned} $$
(6.1)

With equal valued resistors R6–R13 the gain G2nd of the output stage (OPs 3 & 4) becomes 2. Thus, for a given Gamp5 we obtain RG as follows:

$$ {\text{RG}} = \frac{{\text{R4}} + {\text{R5}}}{{{\text{0.5G}}_{{\text{amp5}}} - 1}} $$
(6.2)

Hence, with Gamp5 = 6.25 P1 becomes:

$$ \begin{aligned} {\text{P1}} & = {\text{RG}} - {\text{R3}} \\ & = 1161\,\Omega \\ \end{aligned} $$
(6.3)
Fig. 6.1
figure 1

Circuit of the engine’s output gain stage Amp5, also showing additional offset trim variants

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Fig. 6.2
figure 2

Plug-in connections between PCBs of Amps1, 2, 5 and the mainboard of Fig. 1.17

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The transformer circuit follows the recommendations of Jensen Transformers Inc. Fortunately, switching the transformer in and out of the signal path does not lead to different signal levels. It also does not lower (or lift up) the overall frequency and phase response at the edges of B20k.

On the Mainboard there are three female strip connectors for Amps 1 and 2 and 5. Figure 6.2 shows the connections to the Mainboard and to the plug-in PCBs.

2 Power Supply

Each of the various solid-state gain stages has its own power supply, on plug-in PCBs (Amps 1, 2, and 5) as well as on the Mainboard (Amp4). Figure 6.3 shows the circuit. Because of tolerances of the IC reference voltages R18 and R20 may need additional trimming to get a rather exact ±15 V output.

Fig. 6.3
figure 3

Solid-state gain stage ±15 V PSU

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3 CMRR and Noise

3.1 CMRR

The CMRR reflections follow the remarks I’ve already made about Amp4, hence, with its nominal gain Gamp5 = 6.25 CMRRe of Amp5 becomes appr. 76 dB as follows:

$$ {\text{CMRR}}_{{\text{amp5}}} = \frac{{{\text{G}}_{{\text{amp5}}} }}{{{\text{G}}_{{\text{amp5.cm}}} }} $$
(6.4)
$$ \begin{aligned} {\text{G}}_{{\text{amp5.cm}}} & = 2\frac{{\text{tolerance}}\left[ \% \right]}{200\,\% } \\ & = \frac{2*0.1}{200} \\ & = 0.001 \\ \end{aligned} $$
(6.5)
$$ \begin{aligned} {\text{CMRR}}_{{\text{amp5}}} & = \frac{6.25}{0.001} \\ & = 6250 \\ \end{aligned} $$
(6.6)
$$ \begin{aligned} {\text{CMRR}}_{{\text{amp5.e}}} & = 20\,\log \left( {{\text{CMRR}}_{{\text{amp5}}} } \right) \\ & = 75.92\,{\text{dB}} \\ \end{aligned} $$
(6.7)

Concerning the Amp5 generated common mode noise voltage CMamp5 at the output of its solid-state section we have the same situation already described in Sect. 4.3.6. That’s why it is important to have a well designed following gain stage with a CMRR that is capable to damp CMamp5 to an ignorable amount. The output transformer switched into the signal path produces a big additional CMRRe portion >60 dB. In this context, a transformer is the most effective component.

The next chapter’s Mathcad Worksheet gives the details on Amp5’s CM noise voltage production.

3.2 Noise and SNs

The Mathcad Worksheet 7.1’s noise and SN calculations follow Figs. 6.4 and 6.5 and the calculation course already described for Amp4. However, I’ll repeat the main issues. Additionally, Fig. 6.6 shows the noise situation of the un-balanced output via OP5.

Fig. 6.4
figure 4

Noise sources of Amp5’s input section (OPs 1 & 2)

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Fig. 6.5
figure 5

Noise sources of Amp5’s balanced output section (OPs 3 & 4)

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Fig. 6.6
figure 6

Noise sources of Amp5’s un-balanced output stage (OP5)

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With input shorted and R4 = R5, the frequency dependent output noise voltage density en.o.1st(f) of the 1st gain stage with OPs 1 & 2 becomes:

$$ {\text{e}}_{{\text{n.o.1st}}} \left( {\text{f}} \right) = \sqrt {2\,{\text{e}}_{{\text{n.i.1st}}} \left( {\text{f}} \right)^{2} {\text{G}}_{{\text{1st}}}^{2} + {\text{i}}_{{\text{n.i.1st}}}^{2} \left( {{\text{2R4}}} \right)^{2} + {\text{2e}}_{{\text{n.R4}}}^{2} + {\text{e}}_{{\text{n.RG.o}}}^{2} } $$
(6.8)
$$ {\text{e}}_{{\text{n.RG.o}}} = {\text{e}}_{{\text{n.RG}}} \frac{{\text{2R4}}}{{\text{RG}}} $$
(6.9)

With input shorted and R6–R13 with equal values, we obtain the frequency dependent output noise voltage density en.o.3(f) at the output of OP3:

$$ {\text{e}}_{{\text{n.o.3}}} \left( {\text{f}} \right) = \sqrt {2\left( {1 + \frac{{\text{R11}}}{{\text{R7}}}} \right)\left( {\frac{{{\text{e}}_{{\text{n.i.2nd}}} \left( {\text{f}} \right)^{2} }}{2} + {\text{e}}_{{\text{n.RP.op3}}}^{2} + {\text{i}}_{{\text{n.i.2nd}}}^{2} {\text{RP}}_{{\text{op3}}}^{2} } \right)} $$
(6.10)

The same applies for the output noise of OP4, en.o.4(f). Thus, the output noise voltage density of the 2nd gain stage (input shorted) becomes:

$$ {\text{e}}_{{\text{n.o.2nd}}} \left( {\text{f}} \right) = \sqrt {{\text{e}}_{{\text{n.o.3}}} \left( {\text{f}} \right)^{2} + {\text{e}}_{{\text{n.o.4}}} \left( {\text{f}} \right)^{2} } $$
(6.11)

Hence, Amp5’s balanced output noise voltage density en.o.amp5.bal(f) looks as follows:

$$ {\text{e}}_{{\text{n.o.amp5.bal}}} \left( {\text{f}} \right) = \sqrt {\left( {{\text{e}}_{{\text{n.o.1st}}} {\text{G}}_{{\text{2nd}}} } \right)^{2} + {\text{e}}_{{\text{n.o.2nd}}} \left( f \right)^{2} } $$
(6.12)

The noise situation of the un-balanced output looks a bit different.Footnote 1 With input shorted, RPop5 = R14||R15, and Gop5 = 1 + R15/R14 we obtain en.o.5(f):

$$ {\text{e}}_{{\text{n.o.5}}} \left( {\text{f}} \right) = {\text{G}}_{{\text{op5}}} \sqrt {{\text{e}}_{{\text{n.i.5}}} \left( {\text{f}} \right)^{2} + {\text{i}}_{\text{{n.i.5}}}^{2} {\text{RP}}_{{\text{op5}}}^{2} + {\text{e}}_{{\text{n.RP.op5}}}^{2} } $$
(6.13)

We can now formulate the frequency dependent output noise voltage density en.o.amp5.unbal(f) at Amp5’s un-balanced output, with input of Amp5 shorted:

$$ {\text{e}}_{{\text{n.o.amp5.unbal}}} \left( {\text{f}} \right) = \sqrt {{\text{G}}_{{\text{op5}}}^{2} \left( {{\text{e}}_{{\text{n.o.1st}}} \left( {\text{f}} \right)^{2} + {\text{e}}_{{\text{n.o.4}}} \left( {\text{f}} \right)^{2} } \right) + {\text{e}}_{{\text{n.o.5}}} \left( {\text{f}} \right)^{2} } $$
(6.14)

The noise level of Amp5’s output stage is very low. The output transformer does not significantly add further noise to the active parts. With input shorted at the balanced output the A-weighted SNa.o.amp5.bal becomes a measured (calculated) −103.50 dBV(A) (−104.01 dBV(A)) and the un-balanced output offers an SNa.o.amp5.unbal of −102.90 dBV(A) (−103.29 dBV(A)). With these results we can completely ignore any Amp5 impact on the noise that comes in from the preceding gain stages.

4 Additional Remarks

Concerning THD and IMD Amp5, incl. or excl. output trafo, did not produce additional artefacts that could increase the CLIO generated levels.

A simpler Amp5 configuration would work too, eg OPs 1 & 2 in the typical balanced 2-op-amp configuration, however, without output trafo CMRR would be too low, the one we need here to kill the CM voltage generated by the Amp3 current sink.